MCP6421 datasheet(18/34 Pages) MICROCHIP

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MCP6421

DS25165A-page 18

 2013 Microchip Technology Inc.

4.1.4

NORMAL OPERATION

The input stage of the MCP6421 op amp uses two

differential input stages in parallel. One operates at a

low Common mode input voltage (VCM), while the other

operates at a high VCM. With this topology, the device

operates with a VCM up to 300 mV above VDD and

300 mV below VSS. The input offset voltage is

measured at VCM =VSS – 0.3V and VDD + 0.3V, to

ensure proper operation.

The transition between the input stages occurs when

VCM is near VDD –0.6V (see Figures 2-3 and 2-4). For

the best distortion performance and gain linearity, with

non-inverting gains, avoid this region of operation.

4.2

Rail-to-Rail Output

The output voltage range of the MCP6421 op amp is

0.001V

(typical)

and

5.499V

(typical)

when

RL =100 k is connected to VDD/2 and VDD =5.5V.

Refer to Figures 2-24 and 2-26 for more information.

4.3

Capacitive Loads

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases, and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response, with overshoot and ringing in the step

response. While a unity-gain buffer (G = +1 V/V) is the

most sensitive to the capacitive loads, all gains show

the same general behavior.

When driving large capacitive loads with the MCP6421

op amp (e.g., > 60 pF when G = +1 V/V), a small series

resistor at the output (RISO in Figure 4-5) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitance load.

FIGURE 4-4:

Output Resistor, RISO

Stabilizes Large Capacitive Loads.

Figure 4-5 gives the recommended RISO values for the

different capacitive loads and gains. The x-axis is the

normalized load capacitance (CL/GN), where GN is the

circuit's noise gain. For non-inverting gains, GN and the

Signal Gain are equal. For inverting gains, GN is

1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).

FIGURE 4-5:

Recommended RISO Values

for Capacitive Loads.

After selecting RISO for your circuit, double-check the

resulting

frequency

response

peaking

and

step

response overshoot. Modify RISO’s value until the

response

reasonable.

Bench

evaluation

and

simulations with the MCP6421 SPICE macro model are

very helpful.

4.4

Supply Bypass

The MCP6421 op amp’s power supply pin (VDD for

single-supply) should have a local bypass capacitor

(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high

frequency performance. It can use a bulk capacitor

(i.e., 1 µF or larger) within 100 mm to provide large,

slow currents. This bulk capacitor can be shared with

other analog parts.

4.5

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 1012

. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP6421 op amp’s bias current at +25°C (±1 pA,

typical).

VIN

RISO

VOUT

–

MCP6421

100

1000

10000

100000

1 V/V

2 V/V

≥ 5 V/V

DD = 5.5 V

L = 100 k

1.E-11

1.E-10

1.E-09

1.E-08

1.E-07

Normalized Load Capacitance; C

L/GN (F)

10p

100p

10n

0.1μ

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