LCMXO2-256ZE-2TG100C datasheet(54/106 Pages) LATTICE

54 / 106 page

3-15

DC and Switching Characteristics

MachXO2 Family Data Sheet

Typical Building Block Function Performance – ZE Devices

Pin-to-Pin Performance (LVCMOS25 12mA Drive)

Derating Logic Timing

Logic timing provided in the following sections of the data sheet and the Lattice design tools are worst case num-

bers in the operating range. Actual delays may be much faster. Lattice design tools can provide logic timing num-

bers at a particular temperature and voltage.

Function

-3 Timing

Units

Basic Functions

16-bit decoder

13.9

4:1 MUX

10.9

16:1 MUX

12.0

Function

-3 Timing

Units

Basic Functions

16:1 MUX

191

MHz

16-bit adder

134

MHz

16-bit counter

148

MHz

64-bit counter

MHz

Embedded Memory Functions

1024x9 True-Dual Port RAM

(Write Through or Normal, EBR output registers)

MHz

Distributed Memory Functions

16x4 Pseudo-Dual Port RAM (one PFU)

214

MHz

1. The above timing numbers are generated using the Diamond design tool. Exact performance may vary

with device and tool version. The tool uses internal parameters that have been characterized but are not

tested on every device.

LCMXO2-256ZE-2TG100C 数据表(PDF) 54 Page - Lattice Semiconductor

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