LCMXO2-256ZE-2TG100C datasheet(31/106 Pages) LATTICE

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2-27

Architecture

MachXO2 Family Data Sheet

Hot Socketing

The MachXO2 devices have been carefully designed to ensure predictable behavior during power-up and power-

down. Leakage into I/O pins is controlled to within specified limits. This allows for easy integration with the rest of

the system. These capabilities make the MachXO2 ideal for many multiple power supply and hot-swap applica-

tions.

On-chip Oscillator

Every MachXO2 device has an internal CMOS oscillator. The oscillator output can be routed as a clock to the clock

tree or as a reference clock to the sysCLOCK PLL using general routing resources. The oscillator frequency can be

divided by internal logic. There is a dedicated programming bit and a user input to enable/disable the oscillator. The

oscillator frequency ranges from 2.08 MHz to 133 MHz. The software default value of the Master Clock (MCLK) is

nominally 2.08 MHz. When a different MCLK is selected during the design process, the following sequence takes

place:

Device powers up with a nominal MCLK frequency of 2.08 MHz.

During configuration, users select a different master clock frequency.

The MCLK frequency changes to the selected frequency once the clock configuration bits are received.

If the user does not select a master clock frequency, then the configuration bitstream defaults to the MCLK fre-

quency of 2.08 MHz.

Table 2-14 lists all the available MCLK frequencies.

Table 2-14. Available MCLK Frequencies

Embedded Hardened IP Functions and User Flash Memory

All MachXO2 devices provide embedded hardened functions such as SPI, I

2C and Timer/Counter. MachXO2-640/U

and higher density devices also provide User Flash Memory (UFM). These embedded blocks interface through the

WISHBONE interface with routing as shown in Figure 2-20.

MCLK (MHz, Nominal)

2.08 (default)

9.17

33.25

2.46

10.23

3.17

13.3

44.33

4.29

14.78

53.2

5.54

20.46

66.5

26.6

88.67

8.31

29.56

133

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