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AD7680BRJZ-R2 数据表(PDF) 4 Page - Analog Devices

部件名 AD7680BRJZ-R2
功能描述  3 mW, 100 kSPS, 16-Bit ADC in 6-Lead SOT-23
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7680BRJZ-R2 数据表(HTML) 4 Page - Analog Devices

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AD7680
Rev. A | Page 4 of 24
SPECIFICATIONS1
Table 3. VDD = 2.5 V to 4.096 V, fSCLK = 2.5 MHz, fSAMPLE = 100 kSPS, unless otherwise noted; TA = TMIN to TMAX, unless otherwise noted.
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 10 kHz sine wave
Signal-to-Noise + Distortion (SINAD)2
83
83
dB min
VDD = 4.096 V
82
82
dB min
VDD = 2.5 V to 3.6 V
86
86
dB typ
Signal-to-Noise Ratio (SNR)2
84
84
dB min
VDD = 4.096 V
83
83
dB min
VDD = 2.5 V to 3.6 V
86
86
dB typ
Total Harmonic Distortion (THD) 2
−98
−98
dB typ
Peak Harmonic or Spurious Noise (SFDR)2
−95
−99
dB typ
Intermodulation Distortion (IMD)2
Second-Order Terms
−94
−94
dB typ
Third-Order Terms
−100
−100
dB typ
Aperture Delay
20
10
ns max
Aperture Jitter
30
30
ps typ
Full Power Bandwidth
7
7
MHz typ
@ −3 dB; VDD = 4.096 V
5
5
MHz typ
@ −3 dB; VDD = 2.5 V to 3.6 V
2
2
MHz typ
@ −0.1 dB; VDD = 4.096 V
1.6
1.6
MHz typ
@ −0.1 dB; VDD = 2.5 V to 3.6 V
DC ACCURACY
No Missing Codes
14
15
Bits min
Integral Nonlinearity2
±3.5
±3.5
LSB max
VDD = 4.096 V
±3
±3
LSB max
VDD = 2.5 V to 3.6 V
Offset Error2
±1.25
±1.25
mV max
VDD = 4.096 V
±1.098
±1.098
mV max
VDD = 2.5 V to 3.6 V
Gain Error2
±0.038
±0.038
% FS max
ANALOG INPUT
Input Voltage Ranges
0 to VDD
0 to VDD
V
DC Leakage Current
±0.3
±0.3
μA max
Input Capacitance
30
30
pF typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
2.4
V min
Input Low Voltage, VINL
0.4
0.4
V max
Input Current, IIN
±0.3
±0.3
μA max
Typically 10 nA, VIN = 0 V or VDD
Input Capacitance, CIN2, 3
10
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDD − 0.2
VDD − 0.2
V min
ISOURCE = 200 μA
Output Low Voltage, VOL
0.4
0.4
V max
ISINK = 200 μA
Floating-State Leakage Current
±0.3
±0.3
μA max
Floating-State Output Capacitance2, 3
10
10
pF max
Output Coding
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
8
8
μs max
20 SCLK cycles with SCLK at 2.5 MHz
9.6
9.6
μs max
24 SCLK cycles with SCLK at 2.5 MHz
Track-and-Hold Acquisition Time
1.5
1.5
μs max
Full-scale step input
400
400
ns max
Sine wave input ≤ 10 kHz
Throughput Rate
100
100
kSPS
See the Serial Interface section



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