AD7680BRJZ-R2 datasheet(15/24 Pages) AD

15 / 24 page

AD7680

Rev. A | Page 15 of 24

POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered

down between each conversion, or a series of conversions may

be performed at a high throughput rate, and then the ADC is

powered down for a relatively long duration between these

bursts of several conversions. When the AD7680 is in

power-down, all analog circuitry is powered down.

To enter power-down, the conversion process must be

interrupted by bringing CS high anywhere after the second

falling edge of SCLK and before the 10th falling edge of SCLK

as shown in

. Once

Figure 17

CS has been brought high in this

window of SCLKs, the part enters power-down, the conversion

that was initiated by the falling edge of CS is terminated, and

SDATA goes back into three-state. If CS is brought high before

the second SCLK falling edge, the part remains in normal mode

and will not power down. This avoids accidental power-down

due to glitches on the CS line.

In order to exit this mode of operation and power up the

AD7680 again, a dummy conversion is performed. On the

falling edge of CS, the device begins to power up and continues

to power up as long as CS is held low until after the falling edge

of the 10th SCLK. The device is fully powered up once at least

16 SCLKs (or approximately 6 μs) have elapsed and valid data

results from the next conversion as shown in

. If

Figure 18

CS is

brought high before the 10th falling edge of SCLK, regardless of

the SCLK frequency, the AD7680 goes back into power-down

again. This avoids accidental power-up due to glitches on the

CS line or an inadvertent burst of 8 SCLK cycles while CS is low.

So although the device may begin to power-up on the falling

edge of CS, it powers down again on the rising edge of CS as

long as it occurs before the 10th SCLK falling edge.

SCLK

SDATA

THREE-STATE

Figure 17. Entering Power-Down Mode

110

SDATA

SCLK

INVALID DATA

VALID DATA

THE PART IS FULLY POWERED

UP WITH VIN FULLY ACQUIRED

THE PART BEGINS

TO POWER UP

tPOWER UP

Figure 18. Exiting Power-Down Mode

AD7680BRJZ-R2 数据表(PDF) 15 Page - Analog Devices

AD7680BRJZ-R2 数据表(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

数据表下载