PIC18F87J11_12 datasheet(40/466 Pages) MICROCHIP

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PIC18F87J11 FAMILY

DS39778E-page 40

 2007-2012 Microchip Technology Inc.

3.3.1

CLOCK SOURCE SELECTION

The

System

Clock

Select

bits,

SCS<1:0>

(OSCCON<1:0>), select the clock source. The avail-

able clock sources are the primary clock defined by the

FOSC<2:0> Configuration bits, the secondary clock

(Timer1 oscillator) and the internal oscillator. The clock

source changes after one or more of the bits are written

to, following a brief clock transition interval.

The OSTS (OSCCON<3>) and T1RUN (T1CON<6>)

bits indicate which clock source is currently providing

the device clock. The OSTS bit indicates that the

Oscillator Start-up Timer (OST) has timed out and the

primary clock is providing the device clock in primary

clock modes. The T1RUN bit indicates when the

Timer1 oscillator is providing the device clock in sec-

ondary clock modes. In power-managed modes, only

one of these bits will be set at any time. If neither of

these bits is set, the INTRC is providing the clock, or

the internal oscillator has just started and is not yet

stable.

The IDLEN bit determines if the device goes into Sleep

mode or one of the Idle modes when the SLEEP

instruction is executed.

The use of the flag and control bits in the OSCCON

“Power-Managed Modes”

3.3.1.1

System Clock Selection and Device

Resets

Since the SCSx bits are cleared on all forms of Reset,

this means the primary oscillator defined by the

FOSC<2:0> Configuration bits is used as the primary

clock source on device Resets. This could either be the

internal oscillator block by itself, or one of the other

primary clock sources (HS, EC, HSPLL, ECPLL1/2 or

INTPLL1/2).

In those cases when the internal oscillator block, with-

out PLL, is the default clock on Reset, the Fast RC

Oscillator (INTOSC) will be used as the device clock

source. It will initially start at 4 MHz; the postscaler

selection that corresponds to the Reset value of the

IRCF<2:0> bits (‘110’).

Regardless of which primary oscillator is selected,

INTRC will always be enabled on device power-up. It

serves as the clock source until the device has loaded

its configuration values from memory. It is at this point

that the FOSCx Configuration bits are read and the

oscillator selection of the operational mode is made.

Note that either the primary clock source, or the internal

oscillator, will have two bit setting options for the possible

values of the SCS<1:0> bits at any given time.

3.3.2

OSCILLATOR TRANSITIONS

PIC18F87J11 family devices contain circuitry to

prevent clock “glitches” when switching between clock

sources. A short pause in the device clock occurs dur-

ing the clock switch. The length of this pause is the sum

of two cycles of the old clock source and three to four

cycles of the new clock source. This formula assumes

that the new clock source is stable.

Clock transitions are discussed in greater detail in

Section 4.1.2 “Entering Power-Managed Modes”

Note 1:

The Timer1 oscillator must be enabled to

select the secondary clock source. The

Timer1 oscillator is enabled by setting the

T1OSCEN bit in the Timer1 Control regis-

ter (T1CON<3>). If the Timer1 oscillator is

not enabled, then any attempt to select a

secondary clock source when executing a

SLEEP

instruction will be ignored.

It is recommended that the Timer1

oscillator be operating and stable before

executing the SLEEP instruction or a very

long delay may occur while the Timer1

oscillator starts.

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