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PIC18F87J11 数据表(PDF) 55 Page - Microchip Technology |
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PIC18F87J11 数据表(HTML) 55 Page - Microchip Technology |
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55 / 466 page  2007-2012 Microchip Technology Inc. DS39778E-page 55 PIC18F87J11 FAMILY 5.0 RESET The PIC18F87J11 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Configuration Mismatch (CM) f) Brown-out Reset (BOR) g) RESET Instruction h) Stack Full Reset i) Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. Stack Reset events are covered in Section 6.1.6.4 “Stack Full and Underflow Resets” . WDT Resets are covered in Section 25.2 “Watchdog Timer (WDT)” . A simplified block diagram of the on-chip Reset circuit is shown in Figure 5-1. 5.1 RCON Register Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 “Reset State of Registers” . The RCON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 10.0 “Interrupts”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT External Reset MCLR VDD WDT Time-out VDD Rise Detect PWRT INTRC POR Pulse Chip_Reset Brown-out Reset(1) RESET Instruction Stack Pointer Stack Full/Underflow Reset Sleep ( )_IDLE 32 s Note 1: The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip voltage regulator when there is insufficient source voltage to maintain regulation. PWRT 11-Bit Ripple Counter 66 ms S R Q Configuration Word Mismatch |
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