DAC8043FSZ datasheet(4/16 Pages) AD

4 / 16 page

DAC8043

Rev. E | Page 4 of 16

Parameter

Symbol

Conditions

Min

Typ

Max

Unit

POWER SUPPLY

Supply Voltage

VDD

4.75

5.25

Supply Current

IDD

Digital inputs = VIH or VIL

500

μA

Digital inputs = 0 V or VDD

100

μA

1 ±1/2 LSB = ±0.012% of full scale.

2 All grades are monotonic to 12 bits over temperature.

3 Using internal feedback resistor.

4 Guaranteed by design and not tested.

5 Applies to IOUT; all digital inputs = 0 V.

6 VREF = 10 V; all digital inputs = 0 V.

7 Calculated from worst-case RREF: IZSE (in LSBs) = (RREF × ILKG × 4096)/VREF.

8 Absolute temperature coefficient is less than 300 ppm/°C.

9 IOUT load = 100 Ω , CEXT = 13 pF, digital input = 0 V to VDD or VDD to 0 V. Extrapolated to ½ LSB; tS = propagation delay (tPD) + 9τ

where τ = measured time constant of the final RC decay.

10 VREF = 0 V, all digital inputs = 0 V to VDD or VDD to 0 V.

11 All digit inputs = 0 V.

12 Calculations from en = √4K TRB

where:

K = Boltzmann constant, J/°K,

R = resistance, Ω,

T = resistor temperature, °K,

B = bandwidth, Hz.

13 Digital inputs are CMOS gates; IIN is typically 1 nA at 25°C.

14 Tested at VIN = 0 V or VDD.

WAFER TEST LIMITS

VDD = 5 V, VREF = 10 V; IOUT = GND = 0 V, TA = 25°C.

Table 2.

DAC8043GBC Limit

Parameter1

Symbol

Conditions

Min

Typ

Max

Unit

STATIC ACCURACY

Resolution

Bits

Integral Nonlinearity

INL

±1

LSB

Differential Nonlinearity

DNL

±1

LSB

Gain Error

GFSE

Using internal feedback resistor

±2

LSB

Power Supply Rejection Ratio

PSRR

ΔVDD = ±5%

±0.002

%/%

Output Leakage Current (IOUT)

ILKG

Digital inputs = VIL

±5

REFERENCE INPUT

Input Resistance

RIN

kΩ

DIGITAL INPUTS

Digital Input High

VIH

2.4

Digital Input Low

VIL

0.8

Input Leakage Current

IIL

VIN = 0 V to VDD

±1

μA

POWER SUPPLY

Supply Current

IDD

Digital inputs = VIN or VIL

500

μA

Digital inputs = 0 V or VDD

100

μA

1 Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult a factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

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