DAC8043

Rev. E | Page 10 of 16

DIGITAL SECTION

The digital inputs of the DAC8043 (SRI, LD, and CLK) are TTL

compatible. The input voltage levels affect the amount of current

drawn from the supply; peak supply current occurs as the digital

Maintaining the digital input voltage levels as close as possible

consumption.

The digital inputs of the DAC8043 have been designed with

ESD resistance incorporated through careful layout and the

inclusion of input protection circuitry. Figure 11 shows the input

protection diodes and series resistor; this input structure is

duplicated on each digital input. High voltage static charges

applied to the inputs are shunted to the supply and ground rails

through forward biased diodes. These protection diodes were

designed to clamp the inputs to well below dangerous levels

during static discharge conditions.

GENERAL CIRCUIT INFORMATION

The DAC8043 is a 12-bit multiplying digital-to-analog

converter (DAC) with a very low temperature coefficient.

It contains an R-2R resistor ladder network, data input,

control logic, and two data registers.

TL/TTL/CMOS

INPUTS

Figure 11. Digital Input Protection

The digital circuitry forms an interface in which serial data

can be loaded under microprocessor control into a 12-bit shift

register and then transferred, in parallel, to the 12-bit DAC

register.

A simplified circuit of the DAC8043 is shown in Figure 13,

which has an inverted R-2R ladder network consisting of silicon-

chrome, highly stable (50 ppm/°C) thin-film resistors, and

twelve pairs of NMOS current-steering switches.

or GND; this yields a constant current in each ladder leg, regardless

of digital input code. This constant current results in a constant

any reference voltage or current, ac or dc, that is within the limits

stated in the Absolute Maximum Ratings section.

The twelve output current-steering NMOS FET switches are in

series with each R-2R resistor; they can introduce bit errors if all

the switch on resistance is binarily scaled so that the voltage drop

across each switch remains constant. If, for example, Switch S1 of

Figure 13 was designed with an on resistance of 10 Ω, Switch S2 for

20 Ω, and so on, a constant 5 mV drop would be maintained across

each switch.

BIT 12 LSB

BIT 11

SRI

CLK INPUT

BIT 2

LD

1

2

11

LOAD SERIAL DATA

INTO INPUT REGISTER

LOAD INPUT REGISTER’S

DATA INTO DAC REGISTER

Figure 12. Write Cycle Timing Diagram