M68ICS08GR datasheet(59/408 Pages) FREESCALE

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Low Power Modes

Technical Data

MC68HC908GR8 — Rev 4.0

Low Power Modes

MOTOROLA

•

Low-voltage inhibit (LVI) reset — A power supply voltage below

the LVItripf voltage resets the MCU and loads the program counter

with the contents of locations $FFFE and $FFFF.

•

Break interrupt — A break interrupt loads the program counter

with the contents of locations $FFFC and $FFFD.

•

Timebase module (TBM) interrupt — A TBM interrupt loads the

program counter with the contents of locations $FFDC and $FFDD

when the timebase counter has rolled over. This allows the TBM

to generate a periodic wakeup from stop mode.

Upon exit from stop mode, the system clocks begin running after an

oscillator stabilization delay. A 12-bit stop recovery counter inhibits the

system clocks for 4096 CGMXCLK cycles after the reset or external

interrupt.

The short stop recovery bit, SSREC, in the configuration register

controls the oscillator stabilization delay during stop recovery. Setting

SSREC reduces stop recovery time from 4096 CGMXCLK cycles to 32

CGMXCLK cycles.

NOTE:

Use the full stop recovery time (SSREC = 0) in applications that use an

external crystal.

Freescale Semiconductor, Inc.

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M68ICS08GR 数据表(PDF) 59 Page - Freescale Semiconductor, Inc