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M68ICS08GR 数据表(PDF) 87 Page - Freescale Semiconductor, Inc |
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M68ICS08GR 数据表(HTML) 87 Page - Freescale Semiconductor, Inc |
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87 / 408 page ![]() Analog-to-Digital Converter (ADC) I/O Registers MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Analog-to-Digital Converter (ADC) 87 5.8.2 ADC Data Register One 8-bit result register, ADC data register (ADR), is provided. This register is updated each time an ADC conversion completes. 00 01 1 PTB3/ATD3 00 10 0 PTB4/ATD4 00 10 1 PTB5/ATD5 00 11 0 Reserved 00 11 1 Reserved ↓↓↓ ↓↓ Reserved 11 01 1 Reserved 11 10 0 Reserved 11 10 1 VREFH 11 11 0 VREFL 1 1 1 1 1 ADC power off NOTE: If an unknown channel is selected it should be made clear what value the user will read from the ADC Data Register, unknown or reserved is not specific enough. Table 5-1. Mux Channel Select ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 Input Select Address: $0003D Bit 7 654321 Bit 0 Read: AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 Write: Reset: 00000000 = Unimplemented Figure 5-3. ADC Data Register (ADR) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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