OMAP3530ECBC datasheet(170/264 Pages) TI1

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GPMC_FCLK

gpmc_clk

gpmc_ncsx

gpmc_a[26:17]

gpmc_nbe0_cle

gpmc_nbe1

gpmc_nadv_ale

gpmc_noe

gpmc_a[16:1]_d[15:0]

gpmc_io_dir

gpmc_waitx

Address(MSB)

Valid

Address(LSB)

DataIN

OUT

FA0

FA9

FA10

FA3

FA13

FA29

FA1

FA37

FA12

FA4

FA10

FA0

FA5

030-030

FA15

FA14

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Figure 6-11. GPMC/Multiplexed NOR Flash – Asynchronous Read – Single Word Timing(1)(2)(3)

(1) In gpmc_ncsx, x is equal to 0, 1, 2, 3, 4, 5, 6, or 7. In gpmc_waitx, x is equal to 0, 1, 2, or 3.

(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock

cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active functional clock edge.

FA5 value must be stored inside AccessTime register bit field.

(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

170

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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OMAP3530ECBC 数据表(PDF) 170 Page - Texas Instruments

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