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OMAP3530ECBC 数据表(PDF) 82 Page - Texas Instruments

部件名 OMAP3530ECBC
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC 数据表(HTML) 82 Page - Texas Instruments

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 2-3. Ball Characteristics (CUS Pkg.) (continued)
BALL
BALL TOP [2] PIN NAME [3] MODE [4]
TYPE [5]
BALL RESET BALL RESET RESET REL.
POWER [9]
HYS [10]
BUFFER
PULLUP
BOTTOM [1]
STATE [6]
REL. STATE
MODE [8]
STRENG TH
/DOWN TYPE
[7]
(mA) [11]
[12]
gpio_1
4
IO
safe_mode
7
W16
sys_nirq
0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_0
4
IO
safe_mode
7
AA10
sys_
0
I
Z
I
NA
vdds
Yes
NA
NA
LVCMOS
nrespwron
Y10
sys_
0
IOD
0
1 (PU)
0
vdds
Yes
4
PU/ PD
LVCMOS
nreswarm
gpio_30
4
IO
safe_mode
7
AB12
sys_boot0
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_2
4
IO
safe_mode
7
AC16
sys_boot1
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_3
4
IO
safe_mode
7
AD17
sys_boot2
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_4
4
IO
safe_mode
7
AD18
sys_boot3
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_5
4
IO
safe_mode
7
AC17
sys_boot4
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_dir_dat 1
O
2
gpio_6
4
IO
safe_mode
7
AB16
sys_boot5
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
mmc2_dir_dat 1
O
3
gpio_7
4
IO
safe_mode
7
AA15
sys_boot6
0
I
Z
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_8
4
IO
safe_mode
7
AD23
sys_off_ mode 0
O
0
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_9
4
IO
safe_mode
7
Y7
sys_clkout1
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_10
4
IO
safe_mode
7
AA6
sys_clkout2
0
O
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_186
4
IO
safe_mode
7
AB7
jtag_ntrst
0
I
L
L
0
vdds
Yes
NA
PU/ PD
LVCMOS
AB6
jtag_tck
0
I
L
L
0
vdds
Yes
NA
PU/ PD
LVCMOS
AA7
jtag_rtck
0
O
L
0
0
vdds
Yes
4
PU/ PD
LVCMOS
AA9
jtag_tms_tmsc 0
IO
H
H
0
vdds
Yes
4
PU/ PD
LVCMOS
AB10
jtag_tdi
0
I
H
H
0
vdds
Yes
NA
PU/ PD
LVCMOS
AB9
jtag_tdo
0
O
L
Z
0
vdds
Yes
4
PU/ PD
LVCMOS
AC24
jtag_emu0
0
IO
H
H
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_11
4
IO
safe_mode
7
AD24
jtag_emu1
0
IO
H
H
0
vdds
Yes
4
PU/ PD
LVCMOS
gpio_31
4
IO
TERMINAL DESCRIPTION
82
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