OMAP3530ECBC datasheet(1/264 Pages) TI1

部件名	OMAP3530ECBC

功能描述	OMAP3530/25 Applications Processor: OMAP 3 Architecture

PDF	264 Pages

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制造商	TI1 [Texas Instruments]

网页	http://www.ti.com

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OMAP3530/25 Applications Processor

1.1 Features

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

–

Additional C64x+™ Enhancements

• OMAP3530/25 Applications Processor:

• Protected Mode Operation

–

OMAP™ 3 Architecture

• Exceptions Support for Error Detection

–

MPU Subsystem

and Program Redirection

• Up to 720-MHz ARM Cortex™-A8 Core

• Hardware Support for Modulo Loop

• NEON™ SIMD Coprocessor

Operation

–

High Performance Image, Video, Audio

• C64x+ L1/L2 Memory Architecture

(IVA2.2™) Accelerator Subsystem

–

32K-Byte L1P Program RAM/Cache (Direct

• Up to 520-MHz TMS320C64x+™ DSP

Mapped)

Core

–

80K-Byte L1D Data RAM/Cache (2-Way

• Enhanced Direct Memory Access

Set-Associative)

(EDMA) Controller (128 Independent

–

64K-Byte L2 Unified Mapped RAM/Cache

Channels)

(4-Way Set-Associative)

• Video Hardware Accelerators

–

32K-Byte L2 Shared SRAM and 16K-Byte L2

–

POWERVR SGX™ Graphics Accelerator

ROM

(OMAP3530 Device Only)

• C64x+ Instruction Set Features

• Tile Based Architecture Delivering up to

10 MPoly/sec

–

Byte-Addressable (8-/16-/32-/64-Bit Data)

• Universal Scalable Shader Engine:

–

8-Bit Overflow Protection

Multi-threaded Engine Incorporating

–

Bit-Field Extract, Set, Clear

Pixel and Vertex Shader Functionality

–

Normalization, Saturation. Bit-Counting

• Industry Standard API Support:

–

Compact 16-Bit Instructions

OpenGLES 1.1 and 2.0, OpenVG1.0

–

Additional Instructions to Support Complex

• Fine Grained Task Switching, Load

Multiplies

Balancing, and Power Management

• ARM Cortex™-A8 Core

• Programmable High Quality Image

–

ARMv7 Architecture

Anti-Aliasing

• Trust Zone®

–

Fully Software-Compatible With C64x and

• Thumb®-2

ARM9™

• MMU Enhancements

–

Commercial and Extended Temperature

Grades

–

In-Order, Dual-Issue, Superscalar

Microprocessor Core

• Advanced Very-Long-Instruction-Word (VLIW)

–

NEON™ Multimedia Architecture

TMS320C64x+™ DSP Core

–

Over 2x Performance of ARMv6 SIMD

–

Eight Highly Independent Functional Units

–

Supports Both Integer and Floating Point

• +Six ALUs (32-/40-Bit), Each Supports

SIMD

Single 32-Bit, Dual 16-Bit, or Quad 8-Bit

–

Jazelle® RCT Execution Environment

Arithmetic per Clock Cycle

Architecture

• Two Multipliers Support Four 16 x 16-Bit

–

Dynamic Branch Prediction with Branch

Multiplies (32-Bit Results) per Clock

Target Address Cache, Global History

Cycle or Eight 8 x 8-Bit Multiplies (16-Bit

Buffer, and 8-Entry Return Stack

Results) per Clock Cycle

–

Embedded Trace Macrocell (ETM) Support

–

Load-Store Architecture With Non-Aligned

for Non-Invasive Debug

Support

–

64 32-Bit General-Purpose Registers

• ARM Cortex™-A8 Memory Architecture:

–

Instruction Packing Reduces Code Size

–

16K-Byte Instruction Cache (4-Way

Set-Associative)

–

All Instructions Conditional

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this document.

POWERVR SGX is a trademark of Imagination Technologies Ltd.

OMAP is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

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