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OMAP3530ECBC 数据表(PDF) 58 Page - Texas Instruments

部件名 OMAP3530ECBC
功能描述  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

OMAP3530ECBC 数据表(HTML) 58 Page - Texas Instruments

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OMAP3530/25 Applications Processor
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
www.ti.com
Table 2-2. Ball Characteristics (CBC Pkg.) (continued)
BALL
BALL
BUFFER
PULLUP
BALL
BALL TOP
PIN NAME
RESET REL.
MODE [4]
TYPE [5]
RESET
RESET REL.
POWER [9]
HYS [10]
STRENG TH
/DOWN
IO CELL [13]
BOTTOM [1]
[2]
[3]
MODE [8]
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
gpio_134
4
IO
safe_mode
7
-
U9
NA
mmc2_dat3
0
IO
H
H
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
mcspi3_cs0
1
IO
gpio_135
4
IO
safe_mode
7
-
V10
NA
mmc2_dat4
0
IO
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
mmc2_dir_da
1
O
t0
mmc3_dat0
3
IO
gpio_136
4
IO
safe_mode
7
-
R2
NA
uart1_rts
0
O
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_149
4
IO
safe_mode
7
-
H3
NA
uart1_rx
0
I
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
mcbsp1_clkr
2
IO
mcspi4_clk
3
IO
gpio_151
4
IO
safe_mode
7
-
L4
NA
uart1_tx
0
O
L
L
7
vdds
Yes
4
(3)
PU100/
LVCMOS
PD100
gpio_148
4
IO
safe_mode
7
-
Y24
NA
uart2_cts
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_dx
1
IO
gpt9_pwm_e
2
IO
vt
gpio_144
4
IO
safe_mode
7
-
AA24
NA
uart2_rts
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_dr
1
I
gpt10_pwm_
2
IO
evt
gpio_145
4
IO
safe_mode
7
-
AD21
NA
uart2_rx
0
I
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_fsx
1
IO
gpt8_pwm_e
2
IO
vt
gpio_147
4
IO
safe_mode
7
-
AD22
NA
uart2_tx
0
O
H
H
7
vdds
Yes
4
PU100/
LVCMOS
PD100
mcbsp3_clkx
1
IO
gpt11_pwm_
2
IO
evt
gpio_146
4
IO
safe_mode
7
-
F23
NA
uart3_cts_rct
0
IO
H
H
7
vdds
Yes
4
PU100/
LVCMOS
x
PD100
gpio_163
4
IO
safe_mode
7
-
TERMINAL DESCRIPTION
58
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