OMAP3530ECBC datasheet(176/264 Pages) TI1

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6.4.2

SDRAM Controller Subsystem (SDRC)

6.4.2.1 SDRAM Controller Subsystem Device-Specific Information

6.4.2.2 LPDDR Interface

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

The SDRAM controller subsystem (SDRC) module provides connectivity between the OMAP35x

Applications Processor and external DRAM memory components. The SDRC module only supports

low-power double-data-rate (LPDDR) SDRAM devices. Memory devices can be interfaced to the SDRC

using a stacked-memory approach or through the printed circuit board (PCB). The stacked-memory

approach uses the package on package interface pins (available on CBB & CBC package).

The approach to specifying interface timing for the SDRC memory bus is different than on other interfaces

such as the general-purpose memory controller (GPMC) and the multi-channel buffered serial ports

(McBSPs). For these other interfaces the device timing was specified in terms of data manual

specifications and I/O buffer information specification (IBIS) models.

For the SDRC memory bus, the approach is to specify compatible memory devices and provide the

printed circuit board (PCB) solution and guidelines directly to the user. Texas Instruments (TI) has

performed the simulation and system characterization to ensure all interface timings in this solution are

met.

The LPDDR interface is balled out on the bottom side of all OMAP35x packages and on the top side of

OMAP35x POP packages. The LPDDR interface on the top of the POP package has been designed for

compatibility any POP LPDDR device with a matching footprint and compliance with the JEDEC

LPDDR-266 specification.

This section provides the timing specification for the bottom-side LPDDR interface as a PCB design and

manufacturing specification. The design rules constrain PCB trace length, PCB trace skew, signal

integrity, cross-talk, and signal timing. These rules, when followed, result in a reliable LPDDR memory

system without the need for a complex timing closure process. For more information regarding guidelines

for using this LPDDR specification, see the Understanding TI's PCB Routing Rule-Based DDR Timing

Specification Application Report (literature number SPRAAV0).

6.4.2.2.1 LPDDR Interface Schematic

Figure 6-17 and Figure 6-18 show the LPDDR interface schematics for a LPDDR memory system. The 1

x16 LPDDR system schematic is identical to Figure 6-17 except that the high word LPDDR device is

deleted.

176

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

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