OMAP3530ECBC datasheet(212/264 Pages) TI1

212 / 264 page

OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Table 6-74. McSPI1, 2, and 4 Interface Switching Characteristics – Master Mode(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SM0 1/tc(CLK)

Frequency, mcspix_clk

MHz

tj(CLK)

Cycle jitter(4), mcspix_clk

-200

200

-200

200

SM1

tw(CLK)

Pulse duration, mcspix_clk high or low

0.45*P(5)

0.55*P(5)

0.45*P(

0.55*P(5)

SM4

td(CLKAE-SIMOV)

Delay time, mcspix_clk active edge to mcspix_simo

–2.1

11.3

shifted

SM5

td(CSnA-CLKFE)

Delay time, mcspix_csi active to

Modes 1

A(6) – 3.1

A(6) –

mcspix_clk first edge

and 3

4.4

Modes 0

B(7) – 3.1

B(7) –

and 2

4.4

SM6

td(CLKLE-CSnI)

Delay time, mcspix_clk last edge to

Modes 1

B(7) – 3.1

B(7) –

mcspix_csi inactive

and 3

4.4

Modes 0

A(6) – 3.1

A(6) –

and 2

4.4

SM7

td(CSnAE-SIMOV)

Delay time, mcspix_csi active edge to

Modes 0

5.0

11.3

mcspix_simo shifted

and 2

(1)

Timings are given for a maximum load capacitance of 20 pF for spix_csn signals, 30 pF for spix_clk and spix_simo signals with x = 1 or

2, and 20 pF for spi4_clk and spi4_simo signals.

(2)

In mcspix, x is equal to 1, 2, or 4. In mcspix_csn, n is equal to 0, 1, 2, or 3 for x equal to 1, n is equal to 0 or 1 for x equal to 2 and 4.

(3)

The polarity of mcspix_clk and the active edge (rising or falling) on which mcspix_simo is driven and mcspix_somi is latched is all

software configurable.

(4)

Maximum cycle jitter supported by mcspix_clk input clock.

(5)

P = mcspix_clk clock period

(6)

Case P = 20.8 ns, A = (TCS+0.5)*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). Case P > 20.8 ns, A = TCS*P (TCS is a

bitfield of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x Technical Reference Manual

(TRM) [literature number SPRUF98].

(7)

B = TCS*P (TCS is a bit field of MSPI_CHCONFx[26:25] register). For more information, see the McSPI chapter of the OMAP35x

Technical Reference Manual (TRM) [literature number SPRUF98].

Table 6-75 and Table 6-76 assume testing over the recommended operating conditions (see Figure 6-42).

Table 6-75. McSPI 3 Interface Timing Requirements – Master Mode(1)(2)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

SM2

tsu(SOMIV-CLKAE)

Setup time, mcspi3_somi valid before

1.5

4.3

mcspi3_clk active edge

SM3

th(SOMIV-CLKAE)

Hold time, mcspi3_somi valid after mcspi3_clk

2.8

5.9

active edge

(1)

The input timing requirements are given by considering a rise time and a fall time of 4 ns.

(2)

In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

Table 6-76. McSPI3 Interface Switching Requirements – Master Mode(1)(2)(3)

NO.

PARAMETER

1.15 V

1.0 V

UNIT

MIN

MAX

MIN

MAX

1/SM 1/tc(CLK)

Frequency, mcspix_clk

MHz

tj(CLK)

Cycle jitter(4), mcspix_clk

-200

200

-200

200

(1)

The capacitive load is equivalent to 20 pF.

(2)

In mcspi3_csn, n is equal to 0 or 1. The polarity of mcspi3_clk and the active edge (rising or falling) on which mcspi3_simo is driven and

mcspi3_somi is latched is all software configurable.

(3)

This timing applies to all configurations regardless of McSPI3_CLK polarity and which clock edges are used to drive output data and

capture input data.

(4)

Maximum cycle jitter supported by mcspix_clk input clock.

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

212

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