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OMAP3530ECBC 数据表(PDF) 120 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 120 Page - Texas Instruments |
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120 / 264 page  MPU IVA2 vdd_mpu_iva1domain Core Periph1 vdd_coredomain DPLL_MPU LDO in1.8V out1.2V DualVideoDAC SRAM2 ARRAY SRAM2LDO 0V/1.0V/1.2V SRAM1 ARRAY SRAM1LDO 0V/1.0V/1.2V MMC1 vpp DPLL_CORE LDO in1.8V out1.2V DPLL4 LDO in1.8V out1.2V DPLL_IVA LDO in1.8V out1.2V LDO3 1.0V/1.2V vdds Periph2 DPLL5 LDO in1.8V out1.2V WKUP EMU BandGap BCK MEM vss DLL/DCDL HSDIVIDER LDO eFUSE HSDIVIDER LDO cap_vdd_sram_mpu_iva cap_vdd_sram_core tv_ref (forcapacitor) vssa_dac vdd_mpu_iva vdds_dpll_dll vdds_wkup_bg cap_vdd_wkup vdds_mem vdds_sram OMAP Device vdd_core vdds_mmc1 vdds_dpll_per vdda_dac 030-003 vdds_mmc1a OMAP3530/25 Applications Processor SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 www.ti.com Figure 3-1. OMAP3530/25 Power Domains This power domain segmentation switches off (or places in retention state) domains that are unused while keeping others active. This implementation is based on internal switches that independently control each power domain. A power domain regular logic is attached to one of the device VDD supplies through a primary domain switch. When the primary switch is open, most of the logic supply is off, resulting in a low-leakage state of the domain. Embedded switches are implemented for all power domains except the wake-up domain. This allows the domain to be powered off, if not being used, to give maximum power savings. For more information, see the PRCM chapter of the OMAP35x Technical Reference Manual (TRM) [literature number SPRUFA5]. All domain output signals at the interface between power domains are connected through isolation latch cells. These cells ensure a proper electrical isolation between the domains and an appropriate interface state at the domain boundaries. ELECTRICAL CHARACTERISTICS 120 Submit Documentation Feedback |
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