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OMAP3530ECBC 数据表(PDF) 145 Page - Texas Instruments |
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OMAP3530ECBC 数据表(HTML) 145 Page - Texas Instruments |
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145 / 264 page  OMAP3530/25 Applications Processor www.ti.com SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009 Table 4-18. DPLL3 Clock Frequency Ranges, VDD2 OPP2 (continued) Config 1 Config 2 (83 MHz) (100 MHz) Unit Clock Signal Description Min Max Min Max Output of clock manager (CM), generated using CM: L4_ICLK - 41.5 - 50 MHz CM L3_ICLK and divider. SGX SGX input clock, taken from CM CORE_CLK. - 55.53 - 66.67 MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 83 - 100 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 83 - 50 MHz Table 4-19. DPLL3 Clock Frequency Ranges, VDD2 OPP1(1) Config 1 (40 MHz) Unit Clock Signal Description Min Max CM: CORE_CLK Output of clock manager (CM), generated directly from DPLL3. - 83 MHz CM: L3_ICLK Output of clock manager (CM), generated using DPLL3. - 41.5 MHz Output of clock manager (CM), generated using CM L3_ICLK CM: L4_ICLK - 20.75 MHz and divider. SGX SGX input clock, taken from CM CORE_CLK. - N/A MHz SDRC SDRC input clock, taken from CM L3_ICLK. - 41.5 MHz GPMC GPMC input clock, taken from CM L3_ICLK. - 41.5 MHz (1) Cannot boot in OPP1. If OPP1 is desired, boot in higher OPP then switch to OPP1. Table 4-20 summarizes the DLL characteristics. Table 4-20. DLL Characteristics PARAMETER MIN NOM MAX UNIT COMMENTS Supply voltage vdds_dpll_dll 1.71 1.8 1.89 V Junction operating temperature –40 25 105 °C Input clock frequency 66 120 133 MHz APPLICATION MODE 0 83 120 166 APPLICATION MODE 1 Input load(1) 15 fF Lock time(2) 500 Clocks Relock time 500 ns IDLE to MODEMAXDELAY (Mode transitions through idle mode) 150 372 Clocks IDLE to APPLICATION MODE 1 or 0 1 2 µs IDLE to APPLICATION MODE @133 MHz 1 1.5 µs IDLE to APPLICATION MODE @166 MHz (1) This parameter is design goal and is not tested on silicon. (2) Lock signal would go high from power down within 500 clocks. Lock signal switches to low state when the input clock is switched off after 3 µs. Submit Documentation Feedback CLOCK SPECIFICATIONS 145 |
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