M95M02-DRMN6TP datasheet(22/41 Pages) STMICROELECTRONICS

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Instructions

M95M02-DR

22/41

DocID18203 Rev 8

6.5

Read from Memory Array (READ)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data

Input (D). The address is loaded into an internal address register, and the byte of data at

that address is shifted out, on Serial Data Output (Q).

If Chip Select (S) continues to be driven low, the internal address register is incremented

automatically, and the byte of data at the new address is shifted out.

When the highest address is reached, the address counter rolls over to zero, allowing the

Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a

single READ instruction.

The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip

Select (S) signal can occur at any time during the cycle.

The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

6.6

Write to Memory Array (WRITE)

As shown in Figure 13, to send this instruction to the device, Chip Select (S) is first driven

low. The bits of the instruction byte, address byte, and at least one data byte are then shifted

in, on Serial Data Input (D).

The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input

data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a

period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the

end of which the Write in Progress (WIP) bit is reset to 0.

Figure 12. Read from Memory Array (READ) sequence

AI13878

3456789 10

28 29 30 31 32 33 34 35

22 21

3210

36 37 38

76543

High Impedance

Data Out 1

Instruction

24-bit address

MSB

Data Out 2

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