M95M02-DRMN6TP datasheet(32/41 Pages) STMICROELECTRONICS

32 / 41 page

DC and AC parameters

M95M02-DR

32/41

DocID18203 Rev 8

Table 9. Capacitance

Symbol

Parameter

Test conditions(1)

1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.

Min.

Max.

Unit

COUT

Output capacitance (Q)

VOUT = 0 V

CIN

Input capacitance (D)

VIN = 0 V

Input capacitance (other pins)

VIN = 0 V

Table 10. Cycling performance by groups of four bytes

Symbol

Parameter

Test conditions

Min.

Max.

Unit

Ncycle

Write cycle endurance(1)

1. The Write cycle endurance is defined for groups of four data bytes located at addresses [4*N,

4*N+1, 4*N+2, 4*N+3] where N is an integer. The Write cycle endurance is defined by

characterization and qualification.

≤ 25 °C,

VCC(min) < VCC < VCC(max)

4,000,000

Write cycle(2)

2. A Write cycle is executed when either a Page Write, a Byte Write, a WRSR, a WRID or an LID

instruction is decoded. When using the Byte Write, the Page Write or the WRID instruction,

refer also to Section 6.6.1: Cycling with Error Correction Code (ECC).

TA = 85 °C,

VCC(min) < VCC < VCC(max)

1,200,000

Table 11. Memory cell data retention

Parameter

Test conditions

Min.

Unit

Data retention(1)

1. The data retention behavior is checked in production. The 200-year limit is defined from

characterization and qualification results.

TA = 55 °C

200

Year

M95M02-DRMN6TP 数据表(PDF) 32 Page - STMicroelectronics

M95M02-DRMN6TP 数据表(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载

链接网址

M95M02-DRMN6TP 数据表(PDF) 32 Page - STMicroelectronics

M95M02-DRMN6TP 数据表(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表 下载

链接网址

数据表下载