PCF8574_PCF8574A

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Product data sheet

Rev. 5 — 27 May 2013

5 of 33

NXP Semiconductors

PCF8574; PCF8574A

7.

Functional description

Refer to Figure 1 “Block diagram”.

7.1 Device address

Following a START condition, the bus master must send the address of the slave it is

accessing and the operation it wants to perform (read or write). The address format of the

PCF8574/74A is shown in Figure 6. Slave address pins A2, A1 and A0 are held HIGH or

LOW to choose one of eight slave addresses. To conserve power, no internal pull-up

resistors are incorporated on A2, A1 or A0, so they must be externally held HIGH or LOW.

The last bit of the first byte defines the operation to be performed. When set to logic 1 a

read is selected, while a logic 0 selects a write operation (write operation is shown in

Figure 6).

7.1.1 Address maps

The PCF8574 and PCF8574A are functionally the same, but have a different fixed portion

(A6 to A3) of the slave address. This allows eight of the PCF8574 and eight of the

a. PCF8574

b. PCF8574A

Fig 6.

PCF8574 and PCF8574A slave addresses

R/W

002aad628

0

1

0

0

A2

A1

A0

hardware

selectable

slave address

0

fixed

R/W

002aad629

0

1

1

1

A2

A1

A0

hardware

selectable

slave address

0

fixed

Table 4.

PCF8574 address map

Pin connectivity

Address of PCF8574

Address byte value

7-bit

hexadecimal

address

without R/W

A2

A1

A0

A6

A5

A4

A3

A2

A1

A0 R/W

Write

Read

010

0000

-

40h

41h

20h

010

0001

-

42h

43h

21h

010

0010

-

44h

45h

22h

010

0011

-

46h

47h

23h

010

0100

-

48h

49h

24h

010

0101

-

4Ah

4Bh

25h

010

0110

-

4Ch

4Dh

26h

010

0111

-

4Eh

4Fh

27h