REV. D

AD8002

–10–

THEORY OF OPERATION

A very simple analysis can put the operation of the AD8002, a

current feedback amplifier, in familiar terms. Being a current

feedback amplifier, the AD8002’s open-loop behavior is expressed

as transimpedance,

pedance behaves just as the open-loop voltage gain of a voltage

feedback amplifier, that is, it has a large dc value and decreases

at roughly 6 dB/octave in frequency.

× g

conductance of the input stage. This results in a low open-loop

input impedance at the inverting input, a now familiar result.

Using this amplifier as a follower with gain, Figure 4, basic

analysis yields the following result.

V

V

G

TS

TS

G

R

R

G

R

R

Rg

O

IN

Z

ZIN

IN

m

=×

+×

+

=+

=

≈

()

()

/

1

1

1

2

150

Ω

R1

R2

Figure 4.

Recognizing that G

× R

the first order that bandwidth for this amplifier is independent

of gain (G).

Considering that additional poles contribute excess phase at

high frequencies, there is a minimum feedback resistance below

which peaking or oscillation may result. This fact is used to

parasitic capacitance at the inverting input terminal will also add

can be difficult.

Achieving and maintaining gain flatness of better than 0.1 dB at

frequencies above 10 MHz requires careful consideration of

several issues.

Choice of Feedback and Gain Resistors

The fine scale gain flatness will, to some extent, vary with

feedback resistance. It, therefore, is recommended that once

optimum resistor values have been determined, 1% tolerance

values should be used if it is desired to maintain flatness over a

wide range of production lots. In addition, resistors of different

construction have different associated parasitic capacitance

and inductance. Surface mount resistors were used for the bulk

of the characterization for this data sheet. It is not recommended

that leaded components be used with the AD8002.

Printed Circuit Board Layout Considerations

As expected for a wideband amplifier, PC board parasitics can

affect the overall closed-loop performance. Of concern are

stray capacitances at the output and the inverting input nodes. If

a ground plane is to be used on the same side of the board as

the signal traces, a space (5 mm min) should be left around the

signal lines to minimize coupling. Additionally, signal lines

connecting the feedback and gain resistors should be short

enough so that their associated inductance does not cause high

frequency gain errors. Line lengths on the order of less than

5 mm are recommended. If long runs of coaxial cable are being

driven, dispersion and loss must be considered.

Power Supply Bypassing

Adequate power supply bypassing can be critical when optimiz-

ing the performance of a high-frequency circuit. Inductance in

the power supply leads can form resonant circuits that produce

peaking in the amplifier’s response. In addition, if large current

transients must be delivered to the load, bypass capacitors

(typically greater than 1

µF) will be required to provide the

best settling time and lowest distortion. A parallel combina-

tion of 4.7

µF and 0.1 µF is recommended. Some brands of

electrolytic capacitors will require a small series damping resis-

tor

≈4.7 Ω for optimum results.

DC Errors and Noise

There are three major noise and offset terms to consider in a

current feedback amplifier. For offset errors, refer to the equa-

tion below. For noise error, the terms are root-sum-squared to

give a net output error. In the circuit shown in Figure 5 they

and subsequently multiplied by the noise gain, always appears

is a low 2 nV/

√Hz. At low gains, though, the inverting input

layout and device matching contribute to better offset and

drift specifications for the AD8002 compared to many other

current feedback amplifiers. The typical performance curves in

conjunction with the equations below can be used to predict the

performance of the AD8002 in any application.

VV

R

R

IR

R

R

IR

OUT

IO

F

I

BN

N

F

I

BI

F

=×

+











 ±×

×

+











 ±×

11

Figure 5. Output Offset Voltage