REV. D

AD8002

–14–

Table I. Recommended Component Values

AD8002AN (DIP)

AD8002AR (SOIC)

Gain

Gain

Component

–10

–2

–1

+1

+2

+10

+100

–10

–2

–1

+1

+2

+10

+100

Ω)

499

549

576

1210

750

499

1000

499

499

549

953

681

499

1000

Ω)

49.9

274

576

–

750

54.9

10

49.9

249

549

–

681

54.9

10

Ω)

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

49.9

Ω)*

75

75

0

0

75

75

0

0

Ω)

49.9

49.9

49.9

49.9

49.9

49.9

Ω)

–

61.9

54.9

49.9

49.9

49.9

49.9

–

61.9

54.9

49.9

49.9

49.9

49.9

Small Signal BW (MHz)

270

380

410

600

500

170

17

250

410

410

600

500

170

17

0.1 dB Flatness (MHz)

45

80

130

35

60

24

3

50

100

100

35

90

24

3

AD8002ARM ( SOIC)

Gain

Component

–10

–2

–1

+1

+2

+10

+100

Ω)

499

499

590

1000

681

499

1000

Ω)

49.9

249

590

–

681

54.9

10

Ω)

49.9

49.9

49.9

49.9

49.9

49.9

49.9

Ω)*

75

75

0

0

Ω)

49.9

49.9

49.9

Ω)

–

61.9

49.9

49.9

49.9

49.9

49.9

Small Signal BW (MHz)

270

400

410

600

450

170

19

0.1 dB Flatness (MHz)

60

100

100

35

70

35

3

Layout Considerations

The specified high-speed performance of the AD8002 requires

careful attention to board layout and component selection.

tion are mandatory.

The PCB should have a ground plane covering all unused por-

tions of the component side of the board to provide a low

impedance ground path. The ground plane should be removed

from the area near the input pins to reduce stray capacitance.

Chip capacitors should be used for supply bypassing (see Figure

13). One end should be connected to the ground plane and the

other within 1/8 in. of each power pin. An additional large tanta-

lum electrolytic capacitor (4.7

µF–10 µF) should be connected in

parallel, but not necessarily so close, to supply current for fast,

large-signal changes at the output.

The feedback resistor should be located close to the inverting

input pin in order to keep the stray capacitance at this node to a

minimum. Capacitance variations of less than 1 pF at the invert-

ing input will significantly affect high-speed performance.

Stripline design techniques should be used for long signal traces

(greater than about 1 in.). These should be designed with a

characteristic impedance of 50

Ω or 75 Ω and be properly termi-

nated at each end.

Inverting Configuration

Supply Bypassing

Noninverting Configuration

IN

OUT

C1

0.1 F

C3

10 F

C2

0.1 F

C4

10 F

IN

OUT

*SEE TABLE I

Figure 13. Inverting and Noninverting Configurations