Data Sheet

ADT7320

Rev. 0 | Page 19 of 24

C3

C2

C5

C4

DIN

C7

C6

C1

C0

8-BIT DATA

5

6

78

9

10

11

12

13

14

15

16

SCLK

1

23

4

D6

D5

CS

R/W

REGISTER ADDR

0

0

0

D4

D3

D2

D1

D0

D7

DOUT

8-BIT COMMAND BYTE

0

Figure 17. Reading from an 8-Bit Register

C3

C2

C5

C4

DIN

C7

C6

C1

D2

D1

D0

C0

16-BIT DATA

5

24

6

7

8

9

10

11

12

13

14

15

16

22

23

SCLK

12

3

4

D14

D13

17

CS

R/W

REGISTER ADDR

0

0

0

D12

D11

D10

D9

D8

D7

D15

DOUT

8-BIT COMMAND BYTE

0

Figure 18. Reading from a 16-Bit Register

READING DATA

A read transaction begins when the master writes the command

byte to the ADT7320 with the read/write bit set to 1. The master

then supplies 8 or 16 clock pulses, depending on the addressed

register, and the ADT7320 clocks out data from the addressed

register on the DOUT line. Data is clocked out on the first

falling edge of SCLK following the command byte.

The read transaction finishes when the master pulls CS high.

INTERFACING TO DSPs OR MICROCONTROLLERS

The ADT7320 can be operated with CS used as a frame

synchronization signal. This setup is useful for DSP interfaces. In

this case, the first bit (MSB) is effectively clocked out by CS

because CS normally occurs after the falling edge of SCLK in

DSPs. SCLK can continue to run between data transfers, provided

that the timing values are obeyed.

CS can be tied to ground and the serial interface can operate in

a 3-wire mode. DIN, DOUT, and SCLK are used to communicate

with the ADT7320 in this mode.

For microcontroller interfaces, it is recommended that SCLK

idle high between data transfers.

SERIAL INTERFACE RESET

The serial interface can be reset by writing a series of 1s on the

DIN input. If a Logic 1 is written to the ADT7320 DIN line for

at least 32 serial clock cycles, the serial interface is reset. This

ensures that the interface can be reset to a known state if the

interface is lost due to a software error or a glitch in the system.

A reset returns the interface to the state in which it expects a

write to a communications register. This operation resets the

contents of all registers to their power-on values. Following a

reset, allow a period of 500 μs before addressing the serial

interface.