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ADuCM360BCPZ128-R7 数据表(PDF) 14 Page - Analog Devices

部件名 ADuCM360BCPZ128-R7
功能描述  Low Power, Precision Analog Microcontroller with Dual Sigma-Delta ADCs, ARM Cortex-M3
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADuCM360BCPZ128-R7 数据表(HTML) 14 Page - Analog Devices

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ADuCM360/ADuCM361
Data Sheet
Rev. B | Page 14 of 24
I2C TIMING SPECIFICATIONS
The capacitive load for each I2C bus line (CB) is 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design, but
is not production tested.
Table 10. I2C Timing in Fast Mode (400 kHz)
Parameter
Description
Min
Max
Unit
tL
Serial clock (SCL) low pulse width
1300
ns
tH
SCL high pulse width
600
ns
tSHD
Start condition hold time
600
ns
tDSU
Data setup time
100
ns
tDHD
Data hold time
0
ns
tRSU
Setup time for repeated start
600
ns
tPSU
Stop condition setup time
600
ns
tBUF
Bus free time between a stop condition and a start condition
1.3
s
tR
Rise time for both SCL and serial data (SDA)
20 + 0.1 CB
300
ns
tF
Fall time for both SCL and SDA
20 + 0.1 CB
300
ns
tSUP
Pulse width of suppressed spike
0
50
ns
Table 11. I2C Timing in Standard Mode (100 kHz)
Parameter
Description
Min
Max
Unit
tL
SCL low pulse width
4.7
μs
tH
SCL high pulse width
4.0
ns
tSHD
Start condition hold time
4.7
μs
tDSU
Data setup time
250
ns
tDHD
Data hold time
0
μs
tRSU
Setup time for repeated start
4.0
μs
tPSU
Stop condition setup time
4.0
μs
tBUF
Bus free time between a stop condition and a start condition
4.7
μs
tR
Rise time for both SCL and SDA
1
μs
tF
Fall time for both SCL and SDA
300
ns
SDA (I/O)
tBUF
MSB
LSB
ACK
MSB
1
9
8
1
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
tSUP
tR
tF
tF
tR
tH
tL
tSUP
tDSU
tDHD
tRSU
tDHD
tDSU
tSHD
tPSU
Figure 3. I2C-Compatible Interface Timing



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