Data Sheet

ADuCM360/ADuCM361

Rev. B | Page 19 of 24

Pin No.

Mnemonic

Description

14

VREF+

External Reference Positive Input. An external reference can be applied between the VREF+

and VREF− pins.

15

VREF−

External Reference Negative Input. An external reference can be applied between the VREF+

and VREF− pins.

16

AGND

Analog System Ground Reference Pin.

17

AVDD

Analog System Supply Pin. This pin must be connected to AGND via a 0.1 µF capacitor.

18

AVDD_REG

Internal Analog Regulator Supply Output. This pin must be connected to AGND via a 470 nF

capacitor and to Pin 7, DVDD_REG.

19

DAC

DAC Voltage Output.

20

INT_REF

Internal Reference. This pin must be connected to ground via a 470 nF decoupling capacitor.

21

IREF

Optional Reference Current Resistor Connection for the Excitation Current Sources. The reference

current used for the excitation current sources is set by a low drift (5 ppm/°C) external resistor

connected to this pin.

22

AIN5/IEXC

ADC Analog Input 5/Excitation Current Source. This pin can be configured as a positive or

negative input to either ADC in differential or single-ended mode (AIN5). This pin can also be

configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC).

23

AIN6/IEXC

ADC Analog Input 6/Excitation Current Source. This pin can be configured as a positive or

negative input to either ADC in differential or single-ended mode (AIN6). This pin can also be

configured as the output pin for Excitation Current Source 0 or Excitation Current Source 1 (IEXC).

24

AIN7/VBIAS0/IEXC/EXTREF2IN+

ADC Analog Input 7/Bias Voltage Output/Excitation Current Source/External Reference 2 Positive

Input. This pin can be configured as a positive or negative input to either ADC in differential or

single-ended mode (AIN7). This pin can also be configured as an analog output pin to generate a

bias voltage, VBIAS0 of AVDD_REG/2 (VBIAS0); as the output pin for Excitation Current Source 0 or

Excitation Current Source 1 (IEXC); or as the positive input for External Reference 2 (EXTREF2IN+).

25

AIN8/EXTREF2IN−

ADC Analog Input 8/External Reference 2 Negative Input. This pin can be configured as a

positive or negative input to either ADC in differential or single-ended mode (AIN8). This pin

can also be configured as the negative input for External Reference 2 (EXTREF2IN−).

26

AIN9/DACBUFF+

ADC Analog Input 9/Noninverting Input to the DAC Output Buffer. This pin can be configured

as a positive or negative input to either ADC in differential or single-ended mode (AIN9). This

pin can also be configured as the noninverting input to the DAC output buffer when the DAC

is configured for NPN mode (DACBUFF+).

27

AIN10

ADC Analog Input 10. This pin can be configured as a positive or negative input to either ADC

in differential or single-ended mode.

28

AIN11/VBIAS1

ADC Analog Input 11/Bias Voltage Output. This pin can be configured as a positive or negative

input to either ADC in differential or single-ended mode (AIN11). This pin can also be configured

as an analog output pin to generate a bias voltage, VBIAS1 of AVDD_REG/2 (VBIAS1).

29

P0.0/MISO1

General-Purpose Input/Output P0.0/SPI1 Master Input, Slave Output Pin.

30

P0.1/SCLK1/SCL/SIN

(Data Input for the UART Downloader).

31

P0.2/MOSI1/SDA/SOUT

UART Serial Output (Data Output for the UART Downloader).

32

P0.3/IRQ0/CS1

General-Purpose Input/Output P0.3/External Interrupt Request 0/SPI1 Chip Select Pin (Active

Low).

33

P0.4/RTS/ECLKO

General-Purpose Input/Output P0.4/UART Request-to-Send Signal/External Clock Output Pin

for Test Purposes.

34

P0.5/CTS/IRQ1

General-Purpose Input/Output P0.5/UART Clear-to-Send Signal/External Interrupt Request 1.

35

P0.6/IRQ2/SIN

General-Purpose Input/Output P0.6/External Interrupt Request 2/UART Serial Input.

36

P0.7/POR/SOUT

General-Purpose Input/Output P0.7/Power-On Reset Pin (Active High)/UART Serial Output.

37

IOVDD

Digital System Supply Pin. This pin must be connected to DGND via a 0.1 µF capacitor.

38

P1.0/IRQ3/PWMSYNC/EXTCLK

General-Purpose Input/Output P1.0/External Interrupt Request 3/PWM External Synchronization

Input/External Clock Input Pin.

39

P1.1/IRQ4/PWMTRIP/DTR

General-Purpose Input/Output P1.1/External Interrupt Request 4/PWM External Trip Input/

UART Data Terminal Ready Pin.

40

P1.2/PWM0/RI

General-Purpose Input/Output P1.2/PWM0 Output/UART Ring Indicator Pin.

41

P1.3/PWM1/DSR

General-Purpose Input/Output P1.3/PWM1 Output/UART Data Set Ready Pin.

42

P1.4/PWM2/MISO0

General-Purpose Input/Output P1.4/PWM2 Output/SPI0 Master Input, Slave Output Pin.