STLBC01 datasheet(23/40 Pages) STMICROELECTRONICS

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STLBC01

Host controller interface (HCI)

6.2

HCI SPI transport layer

The STBLC01 features a proprietary HCI SPI transport level which may allow the

host/controller system to reach lower power consumption by using lower clock frequencies.

HCI commands sent and events received over the SPI transport layer are identical to the

ones sent/received over the UART transport level. The STBLC01 supports only slave mode

SPI. The maximal SPI speed is 10 MHz. STBLC01 HCI events are signalled to host thought

the assertion of the IRQ pin. When this occurs, the host sends a clock so that event can be

read. Pin IRQ is also used to inform the host that the STBLC01 has data coming from RF

communication to send. The procedures to read events or data are exactly the same.

6.2.1

SPI interface

The STBLC01 includes a 5-wire, 8-bit, MSB first, Motorola compatible with CPOL=0,

CPHA=0 SPI interface. Only half-duplex transport is supported. The SPI interface is defined

through the following pins:

•

CSN: chip select signal. This signal is active low and it is mandatory, even when only 1

slave device is connected to the host

•

SPI_SCK: SPI clock signal. When CSN is active, the host sends to the controller a

number of clock cycles in multiples of 8 bits during each SPI transaction. When CSN is

not active, the STBLC01 ignores any signal sent to this pin. This allows the host to set

a clock signal to serve other devices

•

SPI_MOSI: Host to controller transfer data line. The host generates data on the

negative edge and samples data on the positive edge of the SPI_SCK signal. SPI data

is sent in byte format, with the most significant bit (MSB) first.

•

SPI_MISO: Controller to the host transfer data line. When CSN is active, controller

generated data on the negative edge and sample data on the positive edge of the

SPI_SCK signal. When CSN is inactive, the controller sets this output in tristate mode.

SPI data is sent in byte format, with the most significant bit (MSB) first.

•

IRQ: Interrupt request. This signal is set by the controller when an event needs to be

sent to the host.

6.2.2

SPI flow control

The STBLC01 features a proprietary flow control for all communications over SPI both from

the host to the controller and from the controller to the host. Each SPI transaction is done for

8 bits of data.

Host to controller flow

When the host needs to communicate with the controller, the following flow is followed:

Host sets the MOSI signal to '1'.

Host activates CSN after 100 ns.

Host polls MISO line. The first polling is done at least 100 ns after CSN is activated.

If MISO = '0' then the controller reception buffer is full and the host is not allowed to

start the transaction.

If MISO = '1' then the controller reception buffer is not full and the host can start the

transaction. After each set of 8 rising edges of SPI_SCK, the host polls the MISO line to

check whether the controller reception buffer is not full. The first polling can be done on

the first SPI_SCK falling edge.

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