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AD7621 数据表(PDF) 4 Page - Analog Devices

部件名 AD7621
功能描述  18-Bit, 5 MSPS PulSAR Differential ADC
PDF  24 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD7621 数据表(HTML) 4 Page - Analog Devices

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AD7960
Data Sheet
Rev. 0 | Page 4 of 24
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
VCM PIN
VCM Output
REF/2
VCM Error
−0.01
+0.01
V
Output Impedance
5.1
kΩ
LVDS I/O (ANSI-644)
Data Format
Serial LVDS twos complement
Differential Output Voltage, VOD
RL = 100 Ω
245
290
454
mV
Common-Mode Output Voltage, VOCM
RL = 100 Ω
9805
1130
1375
mV
Differential Input Voltage, VID
100
650
mV
Common-Mode Input Voltage, VICM
800
1575
mV
POWER SUPPLIES
Specified Performance
VDD1
4.75
5
5.25
V
VDD2
1.71
1.8
1.89
V
VIO
1.71
1.8
1.89
V
Operating Currents6
Static—Not Converting, Internal
Reference Buffer Disabled
Self clocked mode, CNV± in
CMOS mode7
VDD1
8
40
µA
VDD2
8
70
µA
VIO
5
5.3
mA
Static—Not Converting, Internal
Reference Buffer Enabled
Self clocked mode, CNV± in
CMOS mode7
VDD1
2.6
2.9
mA
VDD2
9
72
µA
VIO
4.4
5.3
mA
Converting: Internal Reference Buffer
Disabled
Echoed clock mode, CNV± in
LVDS mode
VDD1
2
2.2
mA
VDD2
11.4
13.5
mA
VIO
9
10.3
mA
Converting: Internal Reference Buffer
Enabled
Echoed clock mode, CNV± in
LVDS mode
VDD1
5.6
6
mA
VDD2
11.4
13.5
mA
VIO
9
10.3
mA
Converting: Internal Reference Buffer
Disabled
Self clocked mode, CNV± in
CMOS mode7
VDD1
2
2.2
mA
VDD2
11.4
13.5
mA
VIO
4.9
5.6
mA
Snooze Mode
VDD1
2
4.1
µA
VDD2
1
40.3
µA
VIO
0.1
4.8
µA
Power-Down
EN3 to EN0 = X000
VDD1
1
2.8
µA
VDD2
1
37.8
µA
VIO
0.2
4.6
µA
Power Dissipation
Static—Not Converting, Internal
Reference Buffer Disabled
Self clocked mode, CNV± in
CMOS mode7
9
10.3
mW
Static—Not Converting, Internal
Reference Buffer Enabled
Self clocked mode, CNV± in
CMOS mode7
21
25
mW



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