AD7960

Data Sheet

Rev. 0 | Page 12 of 24

Figure 23. Zero Error and Gain Error vs. Temperature, REF = 5 V

Figure 24. Input Current (IN+, IN−) vs. Differential Input Voltage, REF = 5 V

Figure 25. Supply Current vs. Temperature, REF = 5 V, Self Clocked Mode,

CNV± in CMOS Mode, Internal Reference Buffer Disabled

Figure 26. Power-Down Current vs. Temperature, REF = 5 V

Figure 27. Supply Current vs. Throughput, Self Clocked Mode, CNV± in CMOS

Mode, Internal Reference Buffer Disabled

0

0.5

1.0

1.5

2.0

2.5

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

ZERO ERROR

GAIN ERROR

–0.7

–0.6

–0.5

–0.4

–0.3

–0.2

–0.1

0

0.1

0.2

0.3

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

DIFFERENTIAL INPUT VOLTAGE (V)

IN+

IN–

0

2

4

6

8

10

12

14

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

VDD1

VDD2

VIO

0

2

4

6

8

10

–40

–20

0

20

40

60

80

TEMPERATURE (°C)

VDD2

VDD1

VIO

0

2

4

6

8

10

12

VDD1

VDD2

VIO

0

1

2

3

4

5

THROUGHPUT (MHz)