DSPIC33FJMC202ESS datasheet(119/330 Pages) MICROCHIP

119 / 330 page

DS70283K-page 119

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

10.6

Peripheral Pin Select

Peripheral pin select configuration enables peripheral

set selection and placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, programmers can better tailor the

microcontroller to their entire application, rather than

trimming the application to fit the device.

The peripheral pin select configuration feature

operates over a fixed subset of digital I/O pins.

Programmers can independently map the input and/or

output of most digital peripherals to any one of these

I/O pins. Peripheral pin select is performed in software,

and generally does not require the device to be

reprogrammed. Hardware safeguards are included that

prevent accidental or spurious changes to the

peripheral mapping, once it has been established.

10.6.1

AVAILABLE PINS

The peripheral pin select feature is used with a range

of up to 26 pins. The number of available pins depends

on the particular device and its pin count. Pins that

support the peripheral pin select feature include the

designation “RPn” in their full pin designation, where

“RP” designates a remappable peripheral and “n” is the

remappable pin number.

10.6.2

CONTROLLING PERIPHERAL PIN

SELECT

Peripheral pin select features are controlled through

two sets of special function registers: one to map

peripheral inputs, and one to map outputs. Because

they are separately controlled, a particular peripheral’s

input and output (if the peripheral has both) can be

placed on any selectable function pin without

constraint.

The association of a peripheral to a peripheral

selectable pin is handled in two different ways,

depending on whether an input or output is being

mapped.

10.6.2.1

Input Mapping

The inputs of the peripheral pin select options are

mapped on the basis of the peripheral. A control

will be mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 10-1

through Register 10-13). Each register contains sets of

5-bit fields, with each set associated with one of the

remappable

peripherals.

Programming

given

peripheral’s bit field with an appropriate 5-bit value

maps the RPn pin with that value to that peripheral. For

any given device, the valid range of values for any bit

field corresponds to the maximum number of peripheral

pin selections supported by the device.

Figure 10-2 illustrates remappable pin selection for

U1RX input.

FIGURE 10-2:

REMAPPABLE MUX

INPUT FOR U1RX

Note:

For input mapping only, the Peripheral Pin

Select (PPS) functionality does not have

priority over the TRISx settings. There-

fore, when configuring the RPn pin for

input, the corresponding bit in the TRISx

(i.e., set to ‘1’).

RP0

RP1

RP2

RP25

U1RX input

U1RXR<4:0>

to peripheral

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