LU82541PI datasheet(13/46 Pages) INTEL

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Networking Silicon — 82541(PI/GI/EI)

3.2.2

Arbitration Signals (2)

3.2.3

Interrupt Signal (1)

3.2.4

System Signals (4)

IDSEL

Initialization Device Select. The Initialization Device Select signal is used by the

82541(PI/GI/EI) as a chip select signal during configuration read and write transactions.

DEVSEL#

STS

Device Select. When the Device Select signal is actively driven by the 82541(PI/GI/

EI), it signals the bus master that it has decoded its address as the target of the current

access. As an input, DEVSEL# indicates whether any device on the bus has been

selected.

VIO

VIO. The VIO signal is a voltage reference for the PCI interface (3.3 V or 5 V PCI

signaling environment). It is used as the clamping voltage.

Note: VIO should be connected to 3.3 V Aux or 5 V Aux in order to be compatible with

the pull-up clamps specification.

Symbol

Type

Name and Function

REQ#

Request Bus. The Request Bus signal is used to request control of the bus from the

arbiter. This signal is point-to-point.

GNT#

Grant Bus. The Grant Bus signal notifies the 82541(PI/GI/EI) that bus access has

been granted. This is a point-to-point signal.

Symbol

Type

Name and Function

INTA#

Interrupt A. Interrupt A is used to request an interrupt of the 82541(PI/GI/EI). It is an

active low, level-triggered interrupt signal.

Symbol

Type

Name and Function

CLK

PCI Clock. The PCI Clock signal provides timing for all transactions on the PCI bus

and is an input to the 82541(PI/GI/EI) device. All other PCI signals, except the Interrupt

A (INTA#) and PCI Reset signal (RST#), are sampled on the rising edge of CLK. All

other timing parameters are defined with respect to this edge.

M66EN

66 MHz Enable. M66EN indicates whether the system bus is enabled for 66MHz.

RST#

PCI Reset. When the PCI Reset signal is asserted, all PCI output signals, except the

Power Management Event signal (PME#), are floated and all input signals are ignored.

The PME# context is preserved, depending on power management settings.

Most of the internal state of the 82541(PI/GI/EI) is reset on the de-assertion (rising

edge) of RST#.

CLK_RUN#

I/O

Clock Run. This signal is used by the system to pause the PCI clock signal. It is used

by the 82541(PI/GI/EI) controller to request the PCI clock. When the CLK_RUN#

feature is disabled, leave this pin unconnected.

Symbol

Type

Name and Function

LU82541PI 数据表(PDF) 13 Page - Intel Corporation

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LU82541PI 数据表(PDF) 13 Page - Intel Corporation

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