ADP1655ACBZ-R7 datasheet(22/24 Pages) AD

22 / 24 page

ADP1655

Rev. 0 | Page 22 of 24

PCB LAYOUT

Poor layout can affect performance, causing electromagnetic

interference (EMI) and electromagnetic compatibility (EMC)

problems, ground bounce, and voltage losses. Poor layout can

also affect regulation and stability. A good layout is implemented

using the following rules and shown in Figure 36:

•

Place the inductor, input capacitor, and output capacitor

close to the IC using short tracks. These components carry

high switching frequencies and large tracks act as antennas.

•

Route the output voltage path away from the inductor and

SW node to minimize noise and magnetic interference.

•

Maximize the size of ground metal on the component side

to help with thermal dissipation.

•

Use a ground plane with several vias connecting to the

component side ground to further reduce noise interfe-

rence on sensitive circuit nodes.

HIGH

POWER

LED

VIN

INDUCTOR

OUTPUT

CAPACITOR

INPUT

CAPACITOR

ADP1655

PGND

HIGH

POWER

LED

PGND

Figure 36. Example Layout of the ADP1655 Driving Two White LEDs

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