DAC8512

–10–

REV. A

Operating the DAC8512 on +12 V or +15 V Supplies Only

Although the DAC8512 has been specified to operate on a

single, +5 V supply, a single +5 V supply may not be available in

many applications. Since the DAC8512 consumes no more than

2.5 mA, maximum, then an integrated voltage reference, such as

the REF02, can be used as the DAC8512 +5 V supply. The

configuration of the circuit is shown in Figure 26. Notice that

the reference’s output voltage requires no trimming because of

the REF02’s excellent load regulation and tight initial output

voltage tolerance. Although the maximum supply current of the

DAC8512 is 2.5 mA, local bypassing of the REF02’s output

with at least 0.1

µF at the DAC’s voltage supply pin is recom-

mended to prevent the DAC’s internal digital circuits from af-

fecting the DAC’s internal voltage reference.

+12V OR +15V

0.1

µF

4

REF02

6

2

0.1

µF

6

2

8

DAC8512

V

OUT

1

5

3

4

7

GND

CS

CLR

LD

SCLK

SDI

V

DD

Figure 26. Operating the DAC8512 on +12 V or +15 V

Supplies Using a REF02 Voltage Reference

Measuring Offset Error

One of the most commonly specified endpoint errors associated

with real world nonideal DACs is offset error.

In most DAC testing, the offset error is measured by applying

the zero-scale code and measuring the output deviation from 0

volt. There are some DACs where offset errors may be present

but not observable at the zero scale because of other circuit limi-

tations (for example, zero coinciding with single-supply ground).

In these DACs, nonzero output at zero code cannot be read as

the offset error. In the DAC8512, for example, the zero-scale

error is specified to be

±3 LSBs. Since zero scale coincides with

zero volt, it is not possible to measure negative offset error.

V

OUT

0.1

µF

200

µA, MAX

V–

6

2

8

DAC8512

1

+5V

CS

CLR

5

3

4

LD

SCLK

SDI

R

7

SET CODE = 000

GND

V

DD

Figure 27. Measuring Zero-Scale or Offset Error

By adding a pull-down resistor from the output of the DAC8412

to a negative supply as shown in Figure 27, offset errors can

now be read at zero code. This configuration forces the output

p-channel MOSFET to source current to the negative supply

thereby allowing the designer to determine in which direction the

offset error appears. The value of the resistor should be such that,

at zero code, current through the resistor is 200

µA, maximum.

Bipolar Output Operation

Although the DAC8512 has been designed for single-supply op-

eration, bipolar operation is achievable using the circuit illus-

trated in Figure 28. The circuit uses a single-supply, rail-to-rail

OP295 op amp and the REF03 to generate the –2.5 V reference

required to level-shift the DAC output voltage. Note that the –

2.5 V reference was generated without the use of precision resis-

tors. The circuit has been configured to provide an output

voltage in the range –5 V

≤ V

OUT

≤ +5 V and is coded in com-

plementary offset binary. Although each DAC LSB corresponds

to 1 mV, each output LSB has been scaled to 2.44 mV. Table

III provides the relationship between the digital codes and out-

put voltage.

The transfer function of the circuit is given by:

R4

R1

+ 2.5

×

R4

R2

and, for the circuit values shown, becomes:

× Digital Code + 5 V

+5V

10

µF

+

0.1

µF

1

8

7

4

3

2

5

6

DAC8512

V

DD

GND

R1

10k

Ω

R2

12.7k

R3

247k

Ω

6

5

4

8

7

–5V

≤ V

+5V

+5V

–5V

A2

P2

10k

Ω

ZERO SCALE

ADJUST

P3

500

Ω

R4

23.7k

Ω

FULL SCALE

ADJUST

–2.5V

CLR

LD

CS

SCLK

SDI

0.1

µF

+5V

REF03

A1

–2.5V

0.01

µF

100

Ω

P1

10k

Ω

2.5V

TRIM

2

6

5

4

2

1

3

A1, A2 = 1/2 OP295

Figure 28. Bipolar Output Operation