MCR03EZPFX1002 datasheet(21/36 Pages) IRF

21 / 36 page

IR3837MPbF

Rev 1.31

When an external resistor divider is connected to

the output as shown in figure 16.

Equation (8) can be rewritten as:

For the calculated values of R8 and R9 see

feedback compensation section.

Bootstrap Capacitor Selection

To drive the Control FET, it is necessary to

supply a gate voltage at least 4V greater than

the voltage at the SW pin, which is connected to

the source of the Control FET . This is achieved

by using a bootstrap configuration, which

comprises the internal bootstrap diode and an

external bootstrap capacitor (C6). The operation

of the circuit is as follows: When the sync FET is

turned on, the capacitor node connected to SW

is pulled down to ground. The capacitor charges

towards V

cc through the internal bootstrap diode

(figure 17), which has a forward voltage drop V

The voltage V

c across the bootstrap capacitor

C6 is approximately given as

When the control FET turns on in the next cycle,

the capacitor node connected to SW rises to the

bus voltage V

in. However, if the value of C6 is

appropriately chosen, the voltage V

c across C6

remains approximately unchanged and the

voltage at the Boot pin becomes:

Application Information

Design Example:

The following example is a typical application for

IR3837. The application circuit is shown on page

27.

Enabling the IR3837

As explained earlier, the precise threshold of

the Enable lends itself well to implementation of

a UVLO for the Bus Voltage as shown in figure

15.

For a typical Enable threshold of V

EN = 1.2 V

For a V

in (min)=10.2V, R1=49.9K and R2=6.8k ohm

is a good choice.

Programming the frequency

For F

s = 600 kHz, select Rt = 23.7 kΩ, using

Table 1.

Output Voltage Programming

Output voltage is programmed by reference

voltage and external voltage divider. The Fb pin

is the inverting input of the error amplifier, which

is internally referenced to 0.6V. The divider ratio

is set to provide 0.6V at the Fb pin when the

output is at its desired value. The output voltage

is defined by using the following equation:

kHz

600

≤

max)

(

transient

load

ΔV

)

for





Fig. 16. Typical application of the IR3837 for

programming the output voltage

(9)

....

..........

ref



















(10)

......

..........





IR3624

VOUT

IR3837

Enable

Vin

(min)

(6)

..........

1.2





)

min

in(

(7)

..........





.....(8)

..........



















ref

Fig. 15. Using Enable pin for UVLO

implementation

(11)

..........

Boot







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