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EP3SE110 数据表(PDF) 80 Page - Altera Corporation

部件名 EP3SE110
功能描述  Stratix III Device Handbook
PDF  341 Pages
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制造商  ALTERA [Altera Corporation]
网页  http://www.altera.com
标志 ALTERA - Altera Corporation

EP3SE110 数据表(HTML) 80 Page - Altera Corporation

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1–70
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
SSTL-15
CLASS I
GCLK
t
su
1.010
0.990
-1.105 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601
ns
t
h
0.964
0.929
1.294
-1.309 -1.430 -1.374 -1.667 -1.348 -1.467 -1.413 -1.704
ns
GCLK
PLL
t
su
-0.836
-0.788
1.674
1.514
1.658
1.589
1.879
1.562
1.703
1.638
1.915
ns
t
h
1.024
1.002
-1.276
1.918
2.223
2.104
2.029
1.917
2.144
2.026
2.076
ns
1.8-V HSTL
CLASS I
GCLK
t
su
0.950
0.917
-1.105 -1.472 -1.722 -1.633 -1.557 -1.461 -1.635 -1.548 -1.601
ns
t
h
-0.836
-0.788
-1.285
1.928
2.241
2.122
2.047
1.928
2.161
2.043
2.093
ns
GCLK
PLL
t
su
1.024
1.002
-1.096 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618
ns
t
h
0.950
0.917
1.285
-1.299 -1.412 -1.356 -1.649 -1.337 -1.450 -1.396 -1.687
ns
1.8-V HSTL
CLASS II
GCLK
t
su
-0.827
-0.776
1.683
1.504
1.640
1.571
1.861
1.551
1.686
1.621
1.898
ns
t
h
1.033
1.014
-1.285
1.928
2.241
2.122
2.047
1.928
2.161
2.043
2.093
ns
GCLK
PLL
t
su
0.941
0.905
-1.096 -1.482 -1.740 -1.651 -1.575 -1.472 -1.652 -1.565 -1.618
ns
t
h
-0.827
-0.776
-1.285
1.938
2.257
2.138
2.063
1.937
2.177
2.059
2.109
ns
1.5-V HSTL
CLASS I
GCLK
t
su
1.033
1.014
-1.182 -1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634
ns
t
h
0.941
0.905
1.585
-1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671
ns
GCLK
PLL
t
su
-0.817
-0.847
1.368
1.494
1.624
1.555
1.845
1.542
1.670
1.605
1.882
ns
t
h
0.931
0.973
-1.182
1.938
2.257
2.138
2.063
1.937
2.177
2.059
2.109
ns
1.5-V HSTL
CLASS II
GCLK
t
su
0.931
0.934
1.585
-1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634
ns
t
h
-0.682
-0.673
1.368
-1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671
ns
GCLK
PLL
t
su
-0.817
-0.847
1.368
1.494
1.624
1.555
1.845
1.542
1.670
1.605
1.882
ns
t
h
0.931
0.973
1.368
1.938
2.257
2.138
2.063
1.937
2.177
2.059
2.109
ns
1.2-V HSTL
CLASS I
GCLK
t
su
0.931
0.934
1.368
-1.492 -1.756 -1.667 -1.591 -1.481 -1.668 -1.581 -1.634
ns
t
h
-0.682
-0.673
1.368
-1.289 -1.396 -1.340 -1.633 -1.328 -1.434 -1.380 -1.671
ns
GCLK
PLL
t
su
-0.811
-0.836
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
t
h
0.925
0.962
1.582
1.801
1.915
1.799
1.814
1.796
1.923
1.804
1.865
ns
1.2-V HSTL
CLASS II
GCLK
t
su
0.937
0.945
1.371
1.505
1.747
1.679
1.951
1.526
1.756
1.693
1.982
ns
t
h
-0.688
-0.684
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
GCLK
PLL
t
su
-0.811
-0.836
-1.185 -1.296 -1.513 -1.460 -1.732 -1.306 -1.513 -1.464 -1.763
ns
t
h
0.925
0.962
1.582
1.801
1.915
1.799
1.814
1.796
1.923
1.804
1.865
ns
3.0-V PCI
GCLK
t
su
0.937
0.945
1.371
1.505
1.747
1.679
1.951
1.526
1.756
1.693
1.982
ns
t
h
-0.688
-0.684
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
ns
GCLK
PLL
t
su
-0.817
-0.847
1.368
1.506
1.750
1.682
1.954
1.525
1.761
1.698
1.987
ns
t
h
0.931
0.973
-1.182 -1.297 -1.516 -1.463 -1.735 -1.305 -1.518 -1.469 -1.768
ns
3.0-V
PCI-X
GCLK
t
su
0.931
0.934
1.585
1.800
1.912
1.796
1.811
1.797
1.918
1.799
1.860
ns
t
h
-0.682
-0.673
1.368
1.506
1.750
1.682
1.954
1.525
1.761
1.698
1.987
ns
GCLK
PLL
t
su
-0.817
-0.847
1.377
1.519
1.765
1.697
1.969
1.534
1.771
1.708
1.997
ns
t
h
0.931
0.973
-1.191 -1.310 -1.531 -1.478 -1.750 -1.314 -1.528 -1.479 -1.778
ns
Table 1–52. EP3SL70 Row Pins Input Timing Parameters (Part 3 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V



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