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EP3SE110 数据表(PDF) 82 Page - Altera Corporation |
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EP3SE110 数据表(HTML) 82 Page - Altera Corporation |
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82 / 341 page  1–72 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics I/O Timing Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation 3.0-V LVCMOS 4mA GCLK tco 3.067 3.067 4.284 4.635 5.091 4.971 5.177 4.635 5.091 4.971 5.177 ns GCLK PLL t co 3.392 3.392 4.766 5.161 5.687 5.545 5.873 5.161 5.687 5.545 5.873 ns 8mA GCLK tco 2.988 2.988 4.160 4.505 4.956 4.836 5.042 4.505 4.956 4.836 5.042 ns GCLK PLL t co 3.313 3.313 4.642 5.032 5.552 5.410 5.763 5.032 5.552 5.410 5.763 ns 12mA GCLK t co 2.981 2.981 4.152 4.498 4.947 4.826 5.034 4.498 4.947 4.826 5.034 ns GCLK PLL t co 3.308 3.308 4.635 5.025 5.544 5.401 5.732 5.025 5.544 5.401 5.732 ns 16mA GCLK t co 2.972 2.972 4.137 4.482 4.932 4.811 5.019 4.482 4.932 4.811 5.019 ns GCLK PLL t co 3.299 3.299 4.621 5.010 5.529 5.386 5.737 5.010 5.529 5.386 5.737 ns 2.5 V 4mA GCLK t co 3.187 3.187 4.490 4.860 5.338 5.218 5.424 4.860 5.338 5.218 5.424 ns GCLK PLL t co 3.514 3.514 4.973 5.388 5.934 5.792 6.081 5.388 5.934 5.792 6.081 ns 8mA GCLK t co 3.090 3.090 4.371 4.735 5.206 5.086 5.292 4.735 5.206 5.086 5.292 ns GCLK PLL tco 3.414 3.414 4.854 5.262 5.802 5.660 5.957 5.262 5.802 5.660 5.957 ns 12mA GCLK t co 3.045 3.045 4.284 4.644 5.110 4.989 5.197 4.644 5.110 4.989 5.197 ns GCLK PLL tco 3.370 3.370 4.767 5.171 5.707 5.564 5.879 5.171 5.707 5.564 5.879 ns 16mA GCLK t co 3.006 3.006 4.245 4.602 5.067 4.946 5.154 4.602 5.067 4.946 5.154 ns GCLK PLL t co 3.332 3.332 4.728 5.129 5.664 5.521 5.822 5.129 5.664 5.521 5.822 ns Table 1–53. EP3SL70 Column Pins Output Timing Parameters (Part 2 of 7) I/O Standard Clock Fast Model C2 C3 C4 C4L I3 I4 I4L Units Industrial Commercial V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V |
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