THS1031CPWR datasheet(30/41 Pages) TI

30 / 41 page

THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

details

The above value for RAIN is derived by noting that the average AIN voltage must equal the bias voltage supplied

by the ac coupling network. The average value of VLAST in equation 13 is thus a constant voltage

VLAST = V(AIN bias) – VM

For an input voltage Vin at the AIN pin,

Qin = (VIN – VLAST) × CS

Provided that f (–3 dB) is much lower than fclk, a constant current flowing over the clock period can approximate

the input charging pulse

IIN

= Qin/tclk

= Qin

× fclk

= (Vin – VLAST) × CS × fclk

The ac input resistance RAIN is then

RAIN = dIin/dVin

= 1 / (dVin / dIin)

= 1 / (CS x fclk)

driving the VREF pin (differential mode)

Figure 35 shows the equivalent load on the VREF pin when driving the internal reference buffer via this pin

(MODE = AVDD/2 and REFSENSE = AVDD).

AVDD

AGND

AVDD + VREF/4

VREF

RIN

14 k

Ω

REFSENSE = AVDD,

Mode =

AVDD

Figure 35. Equivalent Circuit of VREF

The current flowing into IIN is given by

IN +

VREF

* AV

)

Note that the actual IIN may differ from this value by up to 50% due to device-to-device processing variations

and allowing for operating temperature variations.

The user should ensure that VREF is driven from a low noise, low drift source, well-decoupled to analog ground

and capable of driving IIN.

(13)

(14)

(15)

(16)

(17)

THS1031CPWR 数据表(PDF) 30 Page - Texas Instruments

THS1031CPWR 数据表(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41

数据表下载