THS1031

3-V TO 5.5-V, 10-BIT, 30 MSPS

CMOS ANALOG-TO-DIGITAL CONVERTER

SLAS242E – NOVEMBER 1999 – REVISED MARCH 2002

32

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

driving REFTF and REFBF (full external reference mode)

AVDD

AGND

AVDD

AGND

680

Ω

To REFBS

(For Kelvin Connection)

To REFTS

(For Kelvin Connection)

REFTF

REFBF

Figure 38. Equivalent Circuit of REFTF and REFBF Inputs

Note the need for off-chip decoupling.

clamp operation

The clamp voltage output level may be established by an analog voltage on the CLAMPIN pin or by

programming the on-chip clamp DAC.

clamp acquisition time

Figure 39 shows the basic operation of the clamp circuit with the analog input AIN coupled via an RC circuit.

10-Bit

DAC

_

+

CLAMPIN

CLAMP

AIN

RIN

CIN

VCLAMP

Control Register

S/H

VIN

SW1

Figure 39. Schematic of Clamp Circuitry

required to set the dc clamp level at AIN. The charging time required to set the correct clamp voltage is called

t

ACQ +

C

IN

R

IN

In

Vc

Ve

maximum tolerable error depends on the application requirements.

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