USB4604 datasheet(39/71 Pages) SMSC

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USB 2.0 HSIC Hi-Speed 4-Port Hub Controller

Datasheet

SMSC USB4604

Revision 1.0 (06-17-13)

DATASHEET

write operation. Where color is visible in the figure, blue indicates signaling from the I2C master, and

gray indicates signaling from the slave.

In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the

start address for sequential write operation. Every subsequent access is a data write to a data register,

where the register address increments after each access and an ACK from the slave occurs.

Sequential write access is terminated by a Stop condition.

7.2.1.2

Sequential Access Reads

The I2C interface supports direct reading of the device registers. In order to read one or more register

addresses, the starting address must be set by using a write sequence followed by a read. The read

when the last byte has been transferred.

In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the

start address for the subsequent sequential read operation. In the read sequence, every data access

is a data read from a data register where the register address increments after each access. The write

sequence can end with optional Stop (P). If so, the read sequence must begin with a Start (S).

Otherwise, the read sequence must start with a Repeated Start (Sr).

Figure 7.8 shows the format of the read operation. Where color is visible in the figure, blue and gold

indicate signaling from the I2C master, and gray indicates signaling from the slave.

Figure 7.7 I2C Sequential Access Write Format

Figure 7.8 I2C Sequential Access Read Format

7-Bit Slave Address

nnnnnnnn

Data value for

XXXXXX

...

nnnnnnnn

Data value for

XXXXXX + y

xxxxxxxx

Address

(bits 7-0)

7-Bit Slave Address

n n n n n n n n

ACK

for xxxxxxxx

n n n n n n n n

ACK

for xxxxxxxx + 1

...

n n n n n n n n

NACK

If previous write setting up

Stop (P), otherwise it will be

Repeated Start (Sr)

for xxxxxxxx + y

7-Bit Slave Address

xxxxxxxx

Address

(bits 7-0)

Optional. If present, Next

access must have Start(S),

otherwise Repeat Start (Sr)

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