PCF8564AUG datasheet(47/48 Pages) NXP

47 / 48 page

PCF8564A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 3 — 26 August 2013

47 of 48

NXP Semiconductors

PCF8564A

Real time clock and calendar

26. Figures

Fig 1.

Block diagram of PCF8564A . . . . . . . . . . . . . . . . .3

Fig 2.

Pinning diagram of PCF8564A . . . . . . . . . . . . . . .4

Fig 3.

Interrupt scheme . . . . . . . . . . . . . . . . . . . . . . . . . .8

Fig 4.

Voltage low detection . . . . . . . . . . . . . . . . . . . . . . .9

Fig 5.

Data flow for the time function . . . . . . . . . . . . . . .12

Fig 6.

Access time for read/write operations . . . . . . . . .13

Fig 7.

Alarm function block diagram. . . . . . . . . . . . . . . .15

Fig 8.

STOP bit functional diagram . . . . . . . . . . . . . . . .18

Fig 9.

STOP bit release timing . . . . . . . . . . . . . . . . . . . .18

Fig 10. POR override sequence . . . . . . . . . . . . . . . . . . .20

Fig 11. Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Fig 12. Definition of START and STOP conditions. . . . . .21

Fig 13. System configuration . . . . . . . . . . . . . . . . . . . . . .22

Fig 14. Acknowledgment on the I2C-bus . . . . . . . . . . . . .22

Fig 15. Slave address . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 16. Master transmits to slave receiver

(WRITE mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Fig 17. Master reads word after setting word address

(write word address; READ data) . . . . . . . . . . . .24

Fig 18. Master reads slave immediately after first byte

(READ mode) . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Fig 19. Interface watchdog timer . . . . . . . . . . . . . . . . . . .25

Fig 20. Device diode protection diagram . . . . . . . . . . . . .26

Fig 21. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .30

Fig 22. IDD as a function of VDD . . . . . . . . . . . . . . . . . . . .30

Fig 23. IDD as a function of temperature . . . . . . . . . . . . .30

Fig 24. Frequency deviation as a function of VDD . . . . . .30

Fig 25. I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .32

Fig 26. Application diagram . . . . . . . . . . . . . . . . . . . . . . .32

Fig 27. Bare die outline of PCF8564AU/x . . . . . . . . . . . .33

Fig 28. Bare die outline of PCF8564AUG/x . . . . . . . . . . .35

Fig 29. Alignment marks of all PCF8564A types . . . . . . .37

Fig 30. Wafer layout of PCF8564A . . . . . . . . . . . . . . . . .39

Fig 31. Film Frame Carrier (FFC) for 6 inch wafer

(PCF8564AU/10AB/1) . . . . . . . . . . . . . . . . . . . . .40

Fig 32. Film Frame Carrier (FFC) for 8 inch wafer

(PCF8564AUG/12HB/1) . . . . . . . . . . . . . . . . . . .41

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