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H5TQ4G43AFR-RDC 数据表(PDF) 30 Page - Hynix Semiconductor

部件名 H5TQ4G43AFR-RDC
功能描述  4Gb DDR3 SDRAM
PDF  35 Pages
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制造商  HYNIX [Hynix Semiconductor]
网页  http://www.skhynix.com/kor/main.do
标志 HYNIX - Hynix Semiconductor

H5TQ4G43AFR-RDC 数据表(HTML) 30 Page - Hynix Semiconductor

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Rev. 1.0 / Apr. 2013
30
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 33.
Speed Bin
DDR3-1600K
Unit
Note
CL - nRCD - nRP
11-11-11
Parameter
Symbol
min
max
Internal read
command to first data
tAA
13.75
(13.125)5,11
20
ns
ACT to internal read or
write delay time
tRCD
13.75
(13.125)5,11
—ns
PRE command period
tRP
13.75
(13.125)5,11
—ns
ACT to ACT or REF
command period
tRC
48.75
(48.125)5,11
—ns
ACT to PRE command
period
tRAS
35
9 * tREFI
ns
CL = 5
CWL = 5
tCK(AVG)
3.0
3.3
ns
1,2,3,4,8,12,13
CWL = 6, 7 tCK(AVG)
Reserved
ns
4
CL = 6
CWL = 5
tCK(AVG)
2.5
3.3
ns
1,2,3,8
CWL = 6
tCK(AVG)
Reserved
ns
1,2,3,4,8
CWL = 7
tCK(AVG)
Reserved
ns
4
CL = 7
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,4,8
(Optional)5,11
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,8
CWL = 8
tCK(AVG)
Reserved
ns
4
CL = 8
CWL = 5
tCK(AVG)
Reserved
ns
4
CWL = 6
tCK(AVG)
1.875
< 2.5
ns
1,2,3,8
CWL = 7
tCK(AVG)
Reserved
ns
1,2,3,4,8
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 9
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,4,8
(Optional)5,11
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 10
CWL = 5, 6 tCK(AVG)
Reserved
ns
4
CWL = 7
tCK(AVG)
1.5
<1.875
ns
1,2,3,8
CWL = 8
tCK(AVG)
Reserved
ns
1,2,3,4
CL = 11
CWL = 5, 6,7 tCK(AVG)
Reserved
ns
4
CWL = 8
tCK(AVG)
1.25
<1.5
ns
1,2,3
Supported CL Settings
5, 6, 7, 8, 9, 10, 11
nCK
Supported CWL Settings
5, 6, 7, 8
nCK



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