ADP1755ACPZ-R7 datasheet(13/20 Pages) AD

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Data Sheet

ADP1754/ADP1755

Rev. E | Page 13 of 20

CH1 1.0V BW

CH3 1.0V BW

CH2 500mV BW M40.0µs

A CH3

900mV

T 50.40%

VIN

1V/DIV

VOUT

500mV/DIV

1V/DIV

VOUT = 1.5V

CIN = COUT = 4.7µF

Figure 30. Typical PG Behavior vs. VOUT, VIN Rising (VOUT = 1.5 V)

CH1 1.0V BW

CH3 1.0V BW

CH2 500mV BW M40.0µs

A CH3

900mV

T 50.40%

VIN

1V/DIV

VOUT

500mV/DIV

1V/DIV

VOUT = 1.5V

CIN = COUT = 4.7µF

Figure 31. Typical PG Behavior vs. VOUT, VIN Falling (VOUT = 1.5 V)

REVERSE CURRENT PROTECTION FEATURE

The ADP1754/ADP1755 have additional circuitry to protect

against reverse current flow from VOUT to VIN. For a typical

LDO with a PMOS pass device, there is an intrinsic body diode

between VIN and VOUT. When VIN is greater than VOUT, this

diode is reverse-biased. If VOUT is greater than VIN, the intrinsic

diode becomes forward-biased and conducts current from VOUT

to VIN, potentially causing destructive power dissipation. The

reverse current protection circuitry detects when VOUT is greater

than VIN and reverses the direction of the intrinsic diode connec-

tion, reverse-biasing the diode. The gate of the PMOS pass

device is also connected to VOUT, keeping the device off.

Figure 32 shows a plot of the reverse current vs. the VOUT to VIN

differential.

4000

3500

3000

2500

2000

1500

1000

500

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

3.6

VOUT – VIN (V)

Figure 32. Reverse Current vs. VOUT − VIN

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