P1P3800A

http://onsemi.com

3

CLKOUT Diagram

LOW

CLK#

CLK

TIMING Diagram For Glitch Free Operation (For Reference)

(Transition of outputs from any state to any other state)

S4=1, S3=1, S2=1, S1=0

Change Area

S4=1, S3=1, S2=0, S1=1

Change Area

S4=0, S3=0, S2=1, S1=1

PD#

PD#=0

Latency

Latency

Input

Clock

CLKOUT1

CLKOUT2

CLKOUT3

CLKOUT4

Note: Transition to new state will happen after a latency of one output clock cycle after completing the present output clock cycle

Transition to new state will happen after a latency of up to 3 input clock cycles excluding the input cycle where the transition has

occured.

Power Up

CLKOUT

I/P CLK

S1~S4 in any stable

state

Valid Clock according to S1~S4

10mS(min)

Note: Transition to new state will happen after a latency of up to 2 input clock cycles excluding the input cycle where the transition has

occured.