P1P3800A

http://onsemi.com

4

PD# Operation

Valid Clock according to S1~S4

10mS(min)

PD#

I/P CLK

S1~S4 in any stable state

CLKOUT

Note: Transition to new state will happen after a latency of up to 2 input clock cycles excluding the input cycle where the transition has

occured.