AD9952

Rev. B | Page 8 of 28

Pin No.

Mnemonic

I/O

Description

23

DACBP

I

DAC Biasline Decoupling Pin. A 0.1 μF capacitor to AGND is recommended.

24

DAC_R

SET

I

A resistor (3.92 kΩ nominal) connected from AGND to DAC_R

for the DAC.

28

COMP_OUT

O

Comparator Output.

30

COMP_IN

I

Comparator Input.

31

COMP_IN

I

Comparator Complementary Input.

35

PWRDWNCTL

I

Input Pin Used as an External Power-Down Control. See Table 7 for additional information.

36

RESET

I

Active High Hardware Reset Pin. Assertion of the RESET pin forces the AD9952 to the initial state,

as described in the I/O port register map (see Table 5).

37

IOSYNC

I

Asynchronous Active High Reset of the Serial Port Controller. When high, the current I/O

operation is immediately terminated, enabling a new I/O operation to commence once IOSYNC is

returned low. If unused, ground this pin; do not allow this pin to float.

38

SDO

O

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data output. When

operated as a 2-wire serial port, this pin is unused and can be left unconnected.

39

CS

I

This pin functions as an active low chip select that allows multiple devices to share the I/O bus.

40

SCLK

I

This pin functions as the serial data clock for I/O operations.

41

SDIO

I/O

When operating the I/O port as a 3-wire serial port, this pin serves as the serial data input only.

When operated as a 2-wire serial port, this pin is the bidirectional serial data pin.

43

DVDD_I/O

I

Digital Power Supply. For I/O cells only, 3.3 V.

44

SYNC_IN

I

Input signal used to synchronize multiple AD9952s. This input is connected to the SYNC_CLK

output of a master AD9952.

45

SYNC_CLK

O

Clock output pin that serves as a synchronizer for external hardware.

46

OSK

I

Input pin used to control the direction of the shaped on-off keying function when programmed

for operation. OSK is synchronous to the SYNC_CLK pin. When OSK is not programmed, this pin

should be tied to DGND.

Paddle

Exposed Paddle

I

The exposed paddle on the bottom of the package is a ground connection for the DAC and must

be attached to AGND in any board layout. Note that Pin 43, DVDD_I/O, can be powered to 1.8 V or

3.3 V; however, the DVDD pins (Pin 2 and Pin 34) can only be powered to 1.8 V.