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AD9952

Rev. B | Page 17 of 28

CFR1 [6]: Comparator Power-Down Bit

CFR1 [6] = 0 (default). The comparator is enabled for operation.

CFR1 [6] = 1. The comparator is disabled and is in its lowest

power dissipation state.

CFR1 [5]: DAC Power-Down Bit

CFR1 [5] = 0 (default). The DAC is enabled for operation.

CFR1 [5] = 1. The DAC is disabled and is in its lowest power

dissipation state.

CFR1 [4]: Clock Input Power-Down Bit

CFR1 [4] = 0 (default). The clock input circuitry is enabled for

operation.

CFR1 [4] = 1. The clock input circuitry is disabled and the

device is in its lowest power dissipation state.

CFR1 [3]: External Power-Down Mode

CFR1 [3] = 0 (default). Selects the external rapid recovery

power-down mode. In this mode, when the PWRDWNCTL

input pin is high, the digital logic and the DAC digital logic are

powered down. The DAC bias circuitry, PLL, oscillator, and

clock input circuitry are not powered down.

CFR1 [3] = 1. Selects the external full power-down mode. In

this mode, when the PWRDWNCTL input pin is high, all

functions are powered down. This includes the DAC and PLL,

which take a significant amount of time to power up.

CFR1 [2]: Not Used

CFR1 [1]: SYNC_CLK Disable Bit

CFR1 [1] = 0 (default). The SYNC_CLK pin is active.

CFR1 [1] = 1. The SYNC_CLK pin assumes a static Logic 0

state to keep noise generated by the digital circuitry at a

minimum. However, the synchronization circuitry remains

active (internally) to maintain normal device timing.

CFR1 [0]: Not Used, Leave at 0

Control Function Register 2 (CFR2)

The CFR2 bits control the functions, features, and modes of the

AD9952, primarily related to the analog sections of the chip.

CFR2 [23:12]: Not Used

CFR2 [11]: High Speed Sync Enable Bit

CFR2 [11] = 0 (default). The high speed sync enhancement is off.

CFR2 [11] = 1. The high speed sync enhancement is on. This bit

should be set when using the autosynchronization feature for

SYNC_CLK inputs beyond 50 MHz, (200 MSPS SYSCLK). See

the Synchronizing Multiple AD9952S section.

CFR2 [10]: Hardware Manual Sync Enable Bit

CFR2 [10] = 0 (default). The hardware manual sync function is off.

CFR2 [10] = 1. The hardware manual sync function is enabled.

While this bit is set, a rising edge on the SYNC_IN pin causes

the device to advance the SYNC_CLK rising edge by one

REFCLK cycle. Unlike the software manual sync enable bit, this

bit does not self-clear. Once the hardware manual sync mode is

enabled, it stays enabled until this bit is cleared (see the

Synchronizing Multiple AD9952 section).

CFR2 [9]: CRYSTAL OUT Enable Bit

CFR2 [9] = 0 (default). The CRYSTAL OUT pin is inactive.

CFR2 [9] = 1. The CRYSTAL OUT pin is active. When active,

the crystal oscillator circuitry output drives the CRYSTAL OUT

pin, which can be connected to other devices to produce a

reference frequency. The oscillator responds to crystals in the

range of 20 MHz to 30 MHz.

CFR2 [8]: Not Used

CFR2 [7:3]: Reference Clock Multiplier Control Bits

This 5-bit word controls the multiplier value out of the clock-

multiplier (PLL) block. Valid values are 4 decimal to 20 decimal

(0x04 to 0x14). Values entered outside this range bypass the

clock multiplier. See the Phase-Locked Loop (PLL) section).

CFR2 [2]: VCO Range Control Bit

This bit is used to control the range setting on the VCO.

CFR2 [2] = 0 (default). The VCO operates in a range of 100

MHz to 250 MHz.

CFR2 [2] = 1. The VCO operates in a range of 250 MHz to

MHz.

CFR2 [1:0]: Charge Pump Current Control Bits

These bits are used to control the current setting on the charge

pump. The default setting, CFR2 [1:0], sets the charge pump

current to the default value of 75 µA. For each bit added (Bit 01,

Bit 10, and Bit 11), 25 µA of current is added to the charge

pump current: 100 µA, 125 µA, and 150 µA.

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