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数据搜索系统，热门电子元器件搜索 |
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AD9920ABBCZ 数据表(PDF) 74 Page - Analog Devices |
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AD9920ABBCZ 数据表(HTML) 74 Page - Analog Devices |
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74 / 112 page  AD9920A Rev. B | Page 74 of 112 VD HD SUSPEND SYNC 73 5 NOTES 1. THE SYNC RISING EDGE RESETS VD/HD AND COUNTERS TO 0. 2. SYNC POLARITY IS PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). 3. DURING SYNC LOW, ALL INTERNAL COUNTERS ARE RESET AND VD/HD CAN BE SUSPENDED USING THE SYNCSUSPEND REGISTER (ADDR 0x13). 4. THE SYNC RISING EDGE CAUSES THE INTERNAL FIELD DESIGNATOR TO INCREMENT. 5. IF SYNCSUSPEND = 1, VERTICAL CLOCKS, H1 TO H4, AND RG ARE HELD AT THE SAME POLARITY SPECIFIED BY OUT_CONTROL = LOW. 6. IF SYNCSUSPEND = 0, ALL CLOCK OUTPUTS CONTINUE TO OPERATE NORMALLY UNTIL THE SYNC RESET EDGE. FIELD DESIGNATOR H1 TO H4, RG, XV1 TO XV24, VSG, SUBCK Figure 94. Normal SYNC (Default Mode 1) 5 1 2 3 4 1FALLING EDGE RESYNCS THE CIRCUIT TO THE LINE/PIXEL NUMBER 0. VD AND HD INTERNALLY RESYNC. 2RISING EDGE RESETS COUNTERS. 3VD IS DISABLED DURING SYNC. THE REGISTER IS PROGRAMMABLE. 4SCP, HBLK, AND CLPOB ARE HELD AT SEQ0 VALUE. 5XV1 TO XV24 SIGNALS ARE HELD AT THE V-OUTPUT START POLARITY. SYNC VD VDLEN HD SCP XV1 TO XV24 Figure 95. Enhanced SYNC Mode 2 with Vertical Signals Held at VTP Start Value |
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