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AD9850/FSPCB 数据表(PDF) 3 Page - Analog Devices |
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AD9850/FSPCB 数据表(HTML) 3 Page - Analog Devices |
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3 / 20 page  AD9850BRS Parameter Temp Test Level Min Typ Max Unit CMOS LOGIC INPUTS (Including CLKIN) Logic 1 Voltage, 5 V Supply 25 °CI 3.5 V Logic 1 Voltage, 3.3 V Supply 25 °CIV 2.4 V Logic 0 Voltage 25 °CIV 0.8 V Logic 1 Current 25 °CI 12 µA Logic 0 Current 25 °CI 12 µA Input Capacitance 25 °CV 3 pF POWER SUPPLY (AOUT = 1/3 CLKIN) +VS Current @ 62.5 MHz Clock, 3.3 V Supply Full VI 30 48 mA 110 MHz Clock, 3.3 V Supply Full VI 47 60 mA 62.5 MHz Clock, 5 V Supply Full VI 44 64 mA 125 MHz Clock, 5 V Supply Full VI 76 96 mA PDISS @ 62.5 MHz Clock, 3.3 V Supply Full VI 100 160 mW 110 MHz Clock, 3.3 V Supply Full VI 155 200 mW 62.5 MHz Clock, 5 V Supply Full VI 220 320 mW 125 MHz Clock, 5 V Supply Full VI 380 480 mW PDISS Power-Down Mode 5 V Supply Full V 30 mW 3.3 V Supply Full V 10 mW *Tested by measuring output duty cycle variation. Specifications subject to change without notice. TIMING CHARACTERISTICS* AD9850BRS Parameter Temp Test Level Min Typ Max Unit tDS (Data Setup Time) Full IV 3.5 ns tDH (Data Hold Time) Full IV 3.5 ns tWH (W_CLK Minimum Pulse Width High) Full IV 3.5 ns tWL (W_CLK Minimum Pulse Width Low) Full IV 3.5 ns tWD (W_CLK Delay after FQ_UD) Full IV 7.0 ns tCD (CLKIN Delay after FQ_UD) Full IV 3.5 ns tFH (FQ_UD High) Full IV 7.0 ns tFL (FQ_UD Low) Full IV 7.0 ns tCF (Output Latency from FQ_UD) Frequency Change Full IV 18 CLKIN Cycles Phase Change Full IV 13 CLKIN Cycles tFD (FQ_UD Minimum Delay after W_CLK) Full IV 7.0 ns tRH (CLKIN Delay after RESET Rising Edge) Full IV 3.5 ns tRL (RESET Falling Edge after CLKIN) Full IV 3.5 ns tRS (Minimum RESET Width) Full IV 5 CLKIN Cycles tOL (RESET Output Latency) Full IV 13 CLKIN Cycles tRR (Recovery from RESET) Full IV 2 CLKIN Cycles Wake-Up Time from Power-Down Mode 25 °CV 5 µs *Control functions are asynchronous with CLKIN. Specifications subject to change without notice. (VS = 5 V 5% except as noted, RSET = 3.9 k ) REV. H –3– AD9850 |
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