AD9850

–13–

REV. H

DATA (7) –

W CLK

FQ UD

W32 = 0

W33 = 0

W34 = 1

W35 = X

W36 = X

W37 = X

W38 = X

W39 = X

Figure 13. Serial Load Power-Down Sequence

QOUT/

QOUTB

IOUT IOUTB

VINP/

VINN

DIGITAL

IN

DAC Output

Comparator Output

Comparator Input

Digital Inputs

Figure 14. AD9850 I/O Equivalent Circuits

PCB LAYOUT INFORMATION

The AD9850/CGPCB and AD9850/FSPCB evaluation boards

(Figures 15 through 18) represent typical implementations of the

AD9850 and exemplify the use of high frequency/high resolution

design and layout practices. The printed circuit board that contains

the AD9850 should be a multilayer board that allows dedicated

power and ground planes. The power and ground planes should

be free of etched traces that cause discontinuities in the planes. It

is recommended that the top layer of the multilayer board also

contain an interspatial ground plane, which makes ground avail-

able for surface-mount devices. If separate analog and digital

system ground planes exist, they should be connected together at

the AD9850 for optimum results.

Avoid running digital lines under the device because these

couple noise onto the die. The power supply lines to the

AD9850 should use as large a track as possible to provide a low

impedance path and reduce the effects of glitches on the power

supply line. Fast switching signals like clocks should be shielded

with ground to avoid radiating noise to other sections of the

board. Avoid crossover of digital and analog signal paths. Traces

on opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the cir-

cuit board. Use microstrip techniques where possible.

Good decoupling is also an important consideration. The analog

(AVDD) and digital (DVDD) supplies to the AD9850 are

independent and separately pinned out to minimize coupling

between analog and digital sections of the device. All analog

and digital supplies should be decoupled to AGND and DGND,

respectively, with high quality ceramic capacitors. To achieve

best performance from the decoupling capacitors, they should

be placed as close as possible to the device, ideally right up

against the device. In systems where a common supply is used to

drive both the AVDD and DVDD supplies of the AD9850, it is

recommended that the system’s AVDD supply be used.

Analog Devices, Inc. applications engineering support is avail-

able to answer additional questions on grounding and PCB

layout. Call 1-800-ANALOGD or contact us at

www.analog.com/dds.

Evaluation Boards

Two versions of evaluation boards are available for the AD9850,

which facilitate the implementation of the device for bench-

top analysis and serve as a reference for PCB layout. The

AD9850/FSPCB is used in applications where the device is used

primarily as a frequency synthesizer. This version facilitates

connection of the AD9850’s internal D/A converter output to a

50

Ω spectrum analyzer input; the internal comparator on the

AD9850 DUT is not enabled (see Figure 15 for an electrical

schematic of AD9850/FSPCB). The AD9850/CGPCB is used

in applications using the device in the clock generator mode. It

connects the AD9850’s DAC output to the internal comparator

input via a single-ended, 42 MHz low-pass, 5-pole elliptical

filter. This model facilitates the access of the AD9850’s com-

parator output for evaluation of the device as a frequency- and

phase-agile clock source (see Figure 17 for an electrical sche-

matic of AD9850/CGPCB).

Both versions of the AD9850 evaluation board are designed to

interface to the parallel printer port of a PC. The operating

software runs under Microsoft

friendly and intuitive format for controlling the functionality

and observing the performance of the device. The 3.5 inch

floppy provided with the evaluation board contains an execut-

able file that loads and displays the AD9850 function-selection

screen. The evaluation board can be operated with 3.3 V or 5 V

supplies. The evaluation boards are configured at the factory for

an external reference clock input; if the on-board crystal clock

source is used, remove R2.